mb/supermicro: restructure x11ssh-tf to represent a x11 board series

Most of the X11 boards with socket LGA1151 are basically the same boards
with just some minor differences like different NICs (1 GbE, 10 GbE),
number of NICs / PCIe ports etc.

There are about 20 boards that can be added, if there is a community for
testing.

To be able to add more x11 boards easily like x11ssm (see CB:35427) this
restructures the x11ssh tree to represent a "X11 LGA1151 series". There
were multiple suggestions for the structure like grouping by series
(x10, x11, x...), grouping by chipset or by cpu family.

It turned out that there are some "X11 series" boards that are
completely different. Grouping by chipset or cpu family suffers from the
same problem. This is why finally we agreed on grouping by series and
socket ("X11 LGA1151 series").

The structure uses the common baseboard scheme, while there is no "real"
baseboard we know of. By checking images, comparing logs etc. we came to
the conclusion that Supermicro does have some base layout which is only
modified a bit for the different boards.

X11SSH-TF was moved to the variants/ folder with it's gpio.h. As we
expect the other boards to have mostly the same device tree, there is a
common devicetree that gets overridden by each variant's overridetree.

Besides that some very minor modifications happened (formatting, fixing
comments, ...) but not much.

Documentation is reworked in CB:35547

Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35426
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 36 insertions, 0 deletions

diff --git a/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd
new file mode 100644
index 0000000000..a29568072e
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd
@@ -0,0 +1,36 @@
+FLASH 16M {
+	SI_ALL@0x0 0x500000 {
+		SI_DESC@0x0 0x1000
+		SI_ME@0x1000 0x4ff000
+	}
+	SI_BIOS@0x500000 0xb00000 {
+		RW_SECTION_A@0x0 0x33e000 {
+			VBLOCK_A@0x0 0x20000
+			FW_MAIN_A(CBFS)@0x20000 0x31dfc0
+			RW_FWID_A@0x33dfc0 0x40
+		}
+		RW_SECTION_B@0x33e000 0x33e000 {
+			VBLOCK_B@0x0 0x20000
+			FW_MAIN_B(CBFS)@0x20000 0x31dfc0
+			RW_FWID_B@0x33dfc0 0x40
+		}
+		MISC_RW@0x67d000 0x62000 {
+			UNIFIED_MRC_CACHE@0x0 0x20000 {
+				RECOVERY_MRC_CACHE@0x0 0x10000
+				RW_MRC_CACHE@0x10000 0x10000
+			}
+			RW_VPD(PRESERVE)@0x20000 0x2000
+			SMMSTORE(PRESERVE)@0x22000 0x40000
+		}
+		WP_RO@0x6df000 0x421000 {
+			RO_VPD(PRESERVE)@0x0 0x4000
+			RO_SECTION@0x4000 0x41d000 {
+				FMAP@0x0 0x800
+				RO_FRID@0x800 0x40
+				RO_FRID_PAD@0x840 0x7c0
+				GBB@0x1000 0xef000
+				COREBOOT(CBFS)@0xf0000 0x32d000
+			}
+		}
+	}
+}