diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-05 23:00:03 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-10 02:27:53 +0000 |
| commit | 6bc1296cbd9c7dfc0a01e2bf713109ae684c474f (patch) | |
| tree | 8a039d87aa01d03c590aa3d3c92a0431ebfe8778 /src/mainboard/supermicro/x11-lga1151-series/variants | |
| parent | 0bae5a72c52a7e696a3859a88c78372e5cb394b4 (diff) | |
mb/supermicro/x11ssm-f: enable AER for PCIe root ports
Follow vendor and enable Advanced Error Reporting for PCIe root ports.
This enabled the Linux AER driver, which handles PCIe error conditions.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9d9b5afca0ca891e2812445db1d42a46ba16199e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48369
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/supermicro/x11-lga1151-series/variants')
| -rw-r--r-- | src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 549d7d27a3..7757b69b3f 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -54,16 +54,19 @@ chip soc/intel/skylake device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4) register "PcieRpEnable[0]" = "1" register "PcieRpLtrEnable[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5) register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" + register "PcieRpAdvancedErrorReporting[4]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device pci 1d.0 on # PCH PCIe Port 9 register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" device pci 00.0 on # GbE 1 subsystemid 0x15d9 0x1533 end @@ -71,6 +74,7 @@ chip soc/intel/skylake device pci 1d.1 on # PCH PCIe Port 10 register "PcieRpEnable[9]" = "1" register "PcieRpLtrEnable[9]" = "1" + register "PcieRpAdvancedErrorReporting[9]" = "1" device pci 00.0 on # GbE 2 subsystemid 0x15d9 0x1533 end @@ -78,6 +82,7 @@ chip soc/intel/skylake device pci 1d.2 on # PCH PCIe Port 11 register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" + register "PcieRpAdvancedErrorReporting[10]" = "1" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end |