diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-24 01:23:28 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-28 12:57:51 +0000 |
| commit | ddd44f4fe9f45dfcdb2467073b4faf1fdb03ce47 (patch) | |
| tree | b29f7c11360e2d85945960277da46181c83c01fc /src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | |
| parent | 84fde762e7c4e1a8e43194a9444b10b681e1cb50 (diff) | |
mb/supermicro/x11-lga1151-series: restructure and clean up devicetree
Drop zero-value devicetree options and move PcieRpEnable options down to
the corresponding devices.
Test: built with TIMELESS=1; binaries remain identical
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9285d786e973621a732e2627c734adc930e54207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/supermicro/x11-lga1151-series/devicetree.cb')
| -rw-r--r-- | src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index e7b26dc5de..c021372fb9 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -1,10 +1,6 @@ chip soc/intel/skylake - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" - # FSP Configuration - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Disabled" @@ -22,20 +18,6 @@ chip soc/intel/skylake [7] = 1, \ }" - register "SataPortsDevSlp" = "{\ - [0] = 0, \ - [1] = 0, \ - [2] = 0, \ - [3] = 0, \ - [4] = 0, \ - [5] = 0, \ - [6] = 0, \ - [7] = 0, \ - }" - - # superspeed_inter-chip_supplement (SSIC) disabled - register "SsicPortEnable" = "0" - # LPC register "serirq_mode" = "SERIRQ_CONTINUOUS" @@ -46,9 +28,6 @@ chip soc/intel/skylake register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" - # No extra VR mailbox command - register "SendVrMbxCmd" = "0" - # Lock Down register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |