diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-10-21 14:19:04 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-03 08:11:03 +0100 |
| commit | 1aa35c6f6c2f3d3820d574579e929cbafd4304a7 (patch) | |
| tree | e7f6a20ca94317095c8eea789ff8d380f5be5a11 /src/mainboard/supermicro/h8scm | |
| parent | b139b5efcc7f1caf541156fa8d213e3eaf231603 (diff) | |
AGESA: Trace execution with AGESA_EVENTLOG()
Change-Id: I5601ed92ca808603b0a9edad118ca54aa168aceb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7604
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/supermicro/h8scm')
| -rw-r--r-- | src/mainboard/supermicro/h8scm/romstage.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index c67a9265af..2f4c828db5 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/lapic.h" #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> @@ -45,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x30); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ @@ -65,7 +64,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); @@ -80,7 +79,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); } post_code(0x3B); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x3C); nb_Ht_Init(); @@ -95,10 +94,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x42); post_code(0x50); |