Supermicro h8scm: add agesa version of supermicro

Supermicro h8scm has a C32 CPU socket, the details of this board is:
http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-F.cfm
We are planning to replace legacy C32 code with agesa and the h8scm_fam10 do not support
family 15 CPU, so we update this mainboard with this patch.

This code supports memory at 800M Hz of f10 CPU, bu f15 CPU does not has this limitation.
If you want to change the frequency of memory, please edit the macros
"BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT" and "BLDCFG_MEMORY_CLOCK_SELECT"
in src/mainboard/supermicro/h8scm/buildOpts.c

Change-Id: I9ca9e70d7f3e82c07e7d36695bf31008db152afb
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1510
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

1 files changed, 119 insertions, 0 deletions

diff --git a/src/mainboard/supermicro/h8scm/Kconfig b/src/mainboard/supermicro/h8scm/Kconfig
new file mode 100644
index 0000000000..f5efcdd879
--- /dev/null
+++ b/src/mainboard/supermicro/h8scm/Kconfig
@@ -0,0 +1,119 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+if BOARD_SUPERMICRO_H8SCM
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select ARCH_X86
+	select CPU_AMD_AGESA_FAMILY15
+	select CPU_AMD_SOCKET_C32
+	select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX
+	select NORTHBRIDGE_AMD_AGESA_FAMILY15
+	select NORTHBRIDGE_AMD_CIMX_RD890
+	select SOUTHBRIDGE_AMD_CIMX_SB700
+	select SUPERIO_WINBOND_W83627DHG
+	select SUPERIO_NUVOTON_WPCM450
+	select DRIVERS_I2C_W83795
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select HAVE_HARD_RESET
+	select SERIAL_CPU_INIT
+	select HAVE_ACPI_TABLES
+	select BOARD_ROMSIZE_KB_4096
+	select TINY_BOOTBLOCK
+
+config MAINBOARD_DIR
+	string
+	default supermicro/h8scm
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "H8SCM"
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x200000
+
+config MAX_CPUS
+	int
+	default 64
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 16
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool
+	default n
+
+config MEM_TRAIN_SEQ
+	int
+	default 2
+
+config IRQ_SLOT_COUNT
+	int
+	default 11
+
+config RAMTOP
+	hex
+	default 0x1000000
+
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+config STACK_SIZE
+	hex
+	default 0x10000
+
+config RAMBASE
+	hex
+	default 0x200000
+
+config SIO_PORT
+	hex
+	default 0x164E
+	help
+		though UARTs are on the NUVOTON BMC, port 0x164E
+		PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
+
+config DRIVERS_PS2_KEYBOARD
+	bool
+	default y
+
+config WARNINGS_ARE_ERRORS
+	bool
+	default n
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config VGA_BIOS
+	bool
+	default n
+
+config VGA_BIOS_ID
+	string
+	depends on VGA_BIOS
+	default "102b,0532"
+
+endif # BOARD_SUPERMICRO_H8SCM_FAM15