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authorDuncan Laurie <dlaurie@chromium.org>2016-09-12 11:20:27 -0700
committerAaron Durbin <adurbin@chromium.org>2016-09-14 22:23:52 +0200
commit772555a214e023c6e3dd267d296bef23242f3638 (patch)
treed690fa10a4213862390fa4912127560dcbdaf994 /src/mainboard/supermicro/h8qme_fam10
parentdb54bb5e3a09126d51fba407b71cdf05e834c71b (diff)
lpss_i2c: Change handling of controller enable/disable
This change modifies the lpss_i2c driver to behave more like the Linux kernel driver. In particular the controller is only enabled when processing a transaction, and is disabled after. This means that errors in one transaction will not affect later transactions. Also when disabling the controller the code is supposed to wait on the enable bit in the "enable status" register and not in the enable control register. In order to get access to this register the reg map was expanded to include all registers. This was tested with the cr50 TPM driver to ensure that if a transaction does fail that it can be successfully retried instead of the bus being unusable. Change-Id: I43a546d54996ba0f08550a801927b8f7a6690cda Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16589 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/supermicro/h8qme_fam10')
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