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authorUwe Hermann <uwe@hermann-uwe.de>2010-11-21 22:47:22 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-21 22:47:22 +0000
commit7b997053eb2fcde464f5f6a1e5c85d1ffb6b4e32 (patch)
tree5339d014fbd29d3eb27cc82987eb7d655d9d8d1a /src/mainboard/supermicro/h8qme_fam10/romstage.c
parent57b2ff886e0ce2c92820f5722c8031def3ac94cf (diff)
Simplify a few code chunks, fix whitespace and indentation.
Also, remove some less useful comments, some dead code / unused functions. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/supermicro/h8qme_fam10/romstage.c')
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/romstage.c16
1 files changed, 5 insertions, 11 deletions
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index e77b139745..dac57f977b 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -117,6 +117,7 @@ static const u8 spd_addr[] = {
#define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
+
static void write_GPIO(void)
{
pnp_enter_ext_func_mode(GPIO1_DEV);
@@ -156,31 +157,24 @@ static void write_GPIO(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
- u32 bsp_apicid = 0;
- u32 val;
- u32 wants_reset;
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
post_code(0x30);
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
post_code(0x32);