diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-27 06:56:47 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-27 06:56:47 +0000 |
commit | 14e22779625de673569c7b950ecc2753fb915b31 (patch) | |
tree | 14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /src/mainboard/supermicro/h8qme_fam10/romstage.c | |
parent | 0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff) |
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/supermicro/h8qme_fam10/romstage.c')
-rw-r--r-- | src/mainboard/supermicro/h8qme_fam10/romstage.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index aa2081f7df..0d1657a170 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -93,12 +93,12 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #define MCP55_NUM 1 -#define MCP55_USE_NIC 0 +#define MCP55_USE_NIC 0 #define MCP55_USE_AZA 0 #define MCP55_PCI_E_X_0 4 @@ -128,13 +128,13 @@ static void sio_setup(void) smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; + byte |= 0x20; pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); @@ -206,7 +206,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x30); - + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } |