diff options
| author | Kerry Sheh <shekairui@gmail.com> | 2012-02-07 20:33:21 +0800 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2012-02-16 21:22:41 +0100 |
| commit | 134d8a94de060a6d09d663167379d895c0af86fc (patch) | |
| tree | c8bb961618bf631ce8220b57d0a3705a032a9abd /src/mainboard/supermicro/h8qgi | |
| parent | a3f060748b692e50b7e3856ef37a731d3c76451c (diff) | |
HWM: Nuvoton W83795G/ADG HWM support
Supermicro H8QGI-F 1 Unit Chassis contain 9 system Fans,
they are controled by a separate W83795G Hardware Monitor chip.
This patch adds Nuvoton W83795G/ADG HWM support.
Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/569
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/supermicro/h8qgi')
| -rw-r--r-- | src/mainboard/supermicro/h8qgi/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8qgi/devicetree.cb | 8 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8qgi/romstage.c | 6 |
3 files changed, 13 insertions, 2 deletions
diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index e900ea8399..58f56929ac 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS select SOUTHBRIDGE_AMD_CIMX_SB700 select SUPERIO_WINBOND_W83627DHG select SUPERIO_NUVOTON_WPCM450 + select DRIVERS_I2C_W83795 select UDELAY_TSC select BOARD_HAS_FADT select HAVE_BUS_CONFIG diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb index 9d77a73463..8ecf96880e 100644 --- a/src/mainboard/supermicro/h8qgi/devicetree.cb +++ b/src/mainboard/supermicro/h8qgi/devicetree.cb @@ -84,8 +84,8 @@ chip northbridge/amd/agesa/family15/root_complex irq 0x70 = 0x01 #keyboard irq 0x72 = 0x0C #mouse end - #device pnp 2e.6 off # SPI - #end + device pnp 2e.6 off # SPI + end device pnp 2e.307 off # GPIO6 end device pnp 2e.8 off # WDTO#, PLED @@ -106,6 +106,10 @@ chip northbridge/amd/agesa/family15/root_complex device pnp 2e.c off # PECI, SST end end #superio/winbond/w83627dhg + chip drivers/i2c/w83795 + device pnp 5e on #hwm + end + end #drivers/i2c/w83795 end # LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 3 diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index ba8c5e5f6e..d4354fd92f 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -90,6 +90,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x3C); + /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. + * In order to access W83795G/ADG HWM using I2C protocol, + * we select function to SDA, SCL function (or GP33, GP32 function). + */ + w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); + nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ |