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authorKonstantin Aladyshev <aladyshev@nicevt.ru>2013-03-06 21:39:40 +0400
committerMarc Jones <marc.jones@se-eng.com>2013-03-08 07:27:51 +0100
commit4c1e906e36252db3361d7df4c3764b352f53e2f3 (patch)
tree45f08a225516a2d457d51bc8465bdabce3c31817 /src/mainboard/supermicro/h8qgi
parent7fcbbb09fd788a9a1791c2abab96359ce960a2cc (diff)
Supermicro H8QGI: set up right frequency limits for memory controller
According to BKDG: "Memory controller (MCT) and DRAM controllers (DCTs) additions: • Support for 933 MHz (1866 MT/s) MEMCLK frequency." Change-Id: I6f307ce3fcb355d5445f1ea86def73a41b928a57 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2589 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/mainboard/supermicro/h8qgi')
-rw-r--r--src/mainboard/supermicro/h8qgi/buildOpts.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c
index 37ead99b64..7584e4f232 100644
--- a/src/mainboard/supermicro/h8qgi/buildOpts.c
+++ b/src/mainboard/supermicro/h8qgi/buildOpts.c
@@ -94,7 +94,7 @@
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY//1600
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
@@ -110,7 +110,7 @@
#define BLDCFG_ONLINE_SPARE FALSE
#define BLDCFG_BANK_SWIZZLE TRUE
#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY //DDR800_FREQUENCY
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
#define BLDCFG_DQS_TRAINING_CONTROL TRUE
#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
#define BLDCFG_USE_BURST_MODE FALSE