diff options
author | efdesign98 <efdesign98@gmail.com> | 2011-07-20 13:23:04 -0600 |
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committer | Marc Jones <marcj303@gmail.com> | 2011-07-22 19:58:55 +0200 |
commit | 95b6611c18adc8aee9381ebdaf94e99e116db417 (patch) | |
tree | 3d48415b08d510fe3790fc750a22a2bc7081e381 /src/mainboard/supermicro/h8qgi/mainboard.c | |
parent | 3cab93ce8ee8943a9e700535d36e0ceaab87b82e (diff) |
Add the SuperMicro H8QGI platform
This set adds support for the SuperMicro H8QGI mainboard.
It is a publicly available 4 socket board using AMD Family
10 cpus and AMD SR5650 and SB700 bridges.
Change-Id: I196704f79db4c45382559c5ee0619dc8d96ff140
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/108
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/supermicro/h8qgi/mainboard.c')
-rwxr-xr-x | src/mainboard/supermicro/h8qgi/mainboard.c | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c new file mode 100755 index 0000000000..f00b5a048f --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/mainboard.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <boot/tables.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/pci_def.h> +#include "southbridge/amd/sr5650/cmn.h" +#include "chip.h" + +void set_pcie_dereset(void); +void set_pcie_reset(void); + +/** + * + */ +void set_pcie_reset(void) +{ +} + +/** + * Release Resets to PCIe Links + * PCIE_RESET_GPIO1,2,4,5 + */ +void set_pcie_dereset(void) +{ + device_t pcie_core_dev; + + pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + set_htiu_enable_bits(pcie_core_dev, 0xA8, 0x07000707, 0x07000707); + set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x00000007, 0x00000007); +} + + +/************************************************* +* enable the dedicated function in h8qgi board. +*************************************************/ +static void h8qgi_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); +} + +#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1) +int add_mainboard_resources(struct lb_memory *mem) +{ + return 0; +} +#endif + +struct chip_operations mainboard_ops = { + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") + .enable_dev = h8qgi_enable, +}; |