diff options
| author | Kimarie Hoot <kimarie.hoot@se-eng.com> | 2013-03-08 13:54:10 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-20 05:53:47 +0100 |
| commit | eef45f9cfd016343fbcf92b4df5b3d76a39c5136 (patch) | |
| tree | af3a0dcf9652ff0689a724135f33f54be03424fd /src/mainboard/supermicro/h8qgi/devicetree.cb | |
| parent | e4ea2ca18d4764f8c79560d373d548d52532566d (diff) | |
Supermicro H8QGI: Use SPD read code from F15 wrapper
Changes:
- Get rid of the h8qgi mainboard specific code and use the
platform generic function wrapper that was added in change
http://review.coreboot.org/#/c/2777/
AMD Fam15: Add SPD read functions to wrapper code
- Move DIMM addresses into devicetree.cb
Notes:
- The DIMM reads only happen in romstage, so the function is not
available in ramstage. Point the read-SPD callback to a generic
function in ramstage.
- select_socket() and restore_socket() started by duplicating
sp5100_set_gpio() and sp5100_restore_gpio(), which were in
dimmSpd.c. In addition to renaming the functions to more
specifically state their purpose, some cleanup and magic number
reduction was done.
Change-Id: I346ebd8399d4ba3e280576e667fdc62fa75a63b8
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2828
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/supermicro/h8qgi/devicetree.cb')
| -rw-r--r-- | src/mainboard/supermicro/h8qgi/devicetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb index b918d3c385..be9e56427e 100644 --- a/src/mainboard/supermicro/h8qgi/devicetree.cb +++ b/src/mainboard/supermicro/h8qgi/devicetree.cb @@ -124,6 +124,14 @@ chip northbridge/amd/agesa/family15/root_complex device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end #f15 + + register "spdAddrLookup" = " + { + { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 0 + { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 1 + { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 2 + { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 3 + }" end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family15/root_complex |