Mainboard: Supermicro/h8qgi mainboard update

1. Supermicro H8QGI mainboard update to support both family10 Revison D
   processor and family15 model 00-0fh processor in one binary image.
2. RD890/SR56X0 IO hub CIMX wrapper support.
3. SP5100/SB700 southbridge CIMX wrapper support.

Both 8 cores and 16 Cores InterLagos Opteron Processor are
tested on this platform.
Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested.

Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/567
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

1 files changed, 17 insertions, 69 deletions

diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb
index 9afaac77ed..9d77a73463 100755..100644
--- a/src/mainboard/supermicro/h8qgi/devicetree.cb
+++ b/src/mainboard/supermicro/h8qgi/devicetree.cb
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -16,20 +16,18 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
-chip northbridge/amd/agesa/family10/root_complex
+chip northbridge/amd/agesa/family15/root_complex
 	device lapic_cluster 0 on
-		chip cpu/amd/agesa/family10
-			device lapic 0x10 on end
+		chip cpu/amd/agesa/family15
+			device lapic 0x20 on end #f15
+			#device lapic 0x10 on end #f10
 		end
 	end
 	device pci_domain 0 on
 		subsystemid 0x15d9 0xab11 inherit #SuperMicro
-		chip northbridge/amd/agesa/family10 # CPU side of HT root complex
-			device pci 18.0 on end # link 0
-			device pci 18.0 on end # link 1
-			device pci 18.0 on end # link 2
-			device pci 18.0 on # link3 SB on socket0 link 2, on internal Node0 Link 3
-				chip southbridge/amd/sr5650 # Southbridge PCI side of HT Root complex
+		chip northbridge/amd/agesa/family15 # CPU side of HT root complex
+			device pci 18.0 on     # Put IO-HUB at link_num 0, Instead of HT Link topology
+				chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex
 					device pci 0.0 on  end # HT Root Complex 0x9600
 					device pci 0.1 off end # CLKCONFIG
 					device pci 2.0 on  end # GPP1 Port0  x16 SLOT4, 0x5A16
@@ -46,11 +44,10 @@ chip northbridge/amd/agesa/family10/root_complex
 					device pci d.0 on  end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
 					register "gpp1_configuration" = "0"   # Configuration 16:0 default
 					register "gpp2_configuration" = "1"   # Configuration 8:8
-					register "gpp3a_configuration" = "2"   # Configuration 4:1:1:0:0:0
-					#register "gpp3a_configuration" = "11"   # Configuration 1:1:1:1:1:1
+					register "gpp3a_configuration" = "2"   # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1
 					register "port_enable" = "0x2104"
-				end #southbridge/amd/sr5650
-				chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pci bus
+				end #northbridge/amd/cimx/rd890
+				chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus
 					device pci 11.0 on end # SATA
 					device pci 12.0 on end # USB1
 					device pci 12.1 on end # USB1
@@ -59,8 +56,8 @@ chip northbridge/amd/agesa/family10/root_complex
 					device pci 13.1 on end # USB2
 					device pci 13.2 on end # USB2
 					device pci 14.0 on end # SM
-					device pci 14.1 on end # IDE  0x439c
-					device pci 14.2 off end # HDA  0x4383, h8qgi doesnt have codec.
+					device pci 14.1 off end # IDE  0x439c
+					device pci 14.2 off end # HDA  0x4383, h8qgi not have codec.
 					device pci 14.3 on # LPC  0x439d
 						chip superio/winbond/w83627dhg
 							device pnp 2e.0 off #  Floppy
@@ -113,64 +110,15 @@ chip northbridge/amd/agesa/family10/root_complex
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # USB 3
 					register "boot_switch_sata_ide" = "0"   # 0: boot from SATA. 1: IDE
-				end # southbridge/amd/sp5100
+				end # southbridge/amd/cimx/sb700
 			end # device pci 18.0
 
 			device pci 18.1 on end
 			device pci 18.2 on end
 			device pci 18.3 on end
 			device pci 18.4 on end
-
-			device pci 19.0 on end
-			device pci 19.1 on end
-			device pci 19.2 on end
-			device pci 19.3 on end
-			device pci 19.4 on end
-
-
-			device pci 1a.0 on end
-			device pci 1a.0 on end
-			device pci 1a.0 on end
-			device pci 1a.0 on # another 56x0 on socket 1 Link 2, internal Node0 link 3
-			end
-			device pci 1a.1 on end
-			device pci 1a.2 on end
-			device pci 1a.3 on end
-			device pci 1a.4 on end
-
-			device pci 1b.0 on end
-			device pci 1b.1 on end
-			device pci 1b.2 on end
-			device pci 1b.3 on end
-			device pci 1b.4 on end
-
-
-			device pci 1c.0 on end
-			device pci 1c.1 on end
-			device pci 1c.2 on end
-			device pci 1c.3 on end
-			device pci 1c.4 on end
-
-			device pci 1d.0 on end
-			device pci 1d.1 on end
-			device pci 1d.2 on end
-			device pci 1d.3 on end
-			device pci 1d.4 on end
-
-
-			device pci 1e.0 on end
-			device pci 1e.1 on end
-			device pci 1e.2 on end
-			device pci 1e.3 on end
-			device pci 1e.4 on end
-
-			device pci 1f.0 on end
-			device pci 1f.1 on end
-			device pci 1f.2 on end
-			device pci 1f.3 on end
-			device pci 1f.4 on end
-
-		end #chip northbridge/amd/agesa/family10 # CPU side of HT root complex
+			device pci 18.5 on end #f15
+		end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
 	end #pci_domain
-end #northbridge/amd/agesa/family10/root_complex
+end #northbridge/amd/agesa/family15/root_complex