Add supermicro h8dmr fam10 target. This is largely a mashup of the tyan s2912

fam10 and h8dmr k8 targets.

Many, many thanks to Marc, Myles, Patrick and Stepan for all their help with
this, and to Arne for doing the s2912 fam10 port.

Build and boot tested. Abuild tested.

There are a number of outstanding issues and caveats - see src/mainboard/supermicro/h8dmr_fam10/README.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 32 insertions, 0 deletions

diff --git a/src/mainboard/supermicro/h8dmr_fam10/README b/src/mainboard/supermicro/h8dmr_fam10/README
new file mode 100644
index 0000000000..ce030987ca
--- /dev/null
+++ b/src/mainboard/supermicro/h8dmr_fam10/README
@@ -0,0 +1,32 @@
+
+
+There are a number of outstanding issues:
+
+* we don't have the mc_patch_01000086.h CPU ucode file yet which is
+referenced in a comment in src/mainboard/supermicro/h8dmr_fam10/Options.lb.
+AMD has not released it yet. This is not a problem specific to this port.
+
+* I'm seeing toolchain issues. I can't get this tree to compile correctly with
+gcc 4.3 (32 bit) - there is an optimization issue where certain parts of the
+CBFS code execute very slowly. With gcc 3.4 (32 bit) that slowness
+disappears. This is probably not a problem related to this port specifically.
+
+* setting CONFIG_DEFAULT_CONSOLE_LOGLEVEL lower than 8 simply hangs the boot
+shortly after the warm reset triggered by the MCP55 code. I think this too
+might be a toolchain problem (but I see it on gcc 3.4 as well as 4.3).
+
+* during startup, the CPU cores talk through each other on serial for a
+while. Again, not an issue specific to this port.
+
+* to avoid very slow LZMA decompression I use this port with LZMA compression
+disabled in CBFS. I'm not sure what's causing this particular slowness.
+
+See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/052107.html
+
+Ward, 2009-09-22
+
+mansoor@iwavesystems.com said, about the last issue:
+
+  Try enabling CONFIG_XIP_ROM_BASE.  It solved the same problem for me in my board.
+
+So, that's a todo.