diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-25 18:06:32 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-25 18:06:32 +0000 |
commit | bcb8c97af94c9fc814fdbdafe5361666bf81d442 (patch) | |
tree | d3a121678b32d7436787975292432c4975bb9f6d /src/mainboard/supermicro/h8dmr | |
parent | 14b62da01ded297e12db6ed3b41778202e9aae41 (diff) |
try to unify timing initialization across those boards that need it...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/supermicro/h8dmr')
-rw-r--r-- | src/mainboard/supermicro/h8dmr/romstage.c | 20 |
1 files changed, 7 insertions, 13 deletions
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 28332dca5d..fd0634ff62 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -49,16 +49,14 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -// for enable the FAN -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" - #include "pc80/serial.c" #include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> -//#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +// for enable the FAN +#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -213,12 +211,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if SET_FIDVID == 1 - { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - + printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -231,12 +227,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - + printk(BIOS_DEBUG, "end msr fid, vid %08x, %08x\n", msr.hi, msr.lo); } #endif -#if 1 + init_timer(); // Need to use TMICT to synconize FID/VID + needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); @@ -246,7 +242,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_info("ht reset -\n"); soft_reset(); } -#endif + allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl in sysinfo now; @@ -254,9 +250,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // enable_smbus(); /* enable in sio_setup */ - //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |