Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

7 files changed, 46 insertions, 46 deletions

diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c
index 60dd1b275e..3454cae313 100644
--- a/src/mainboard/supermicro/h8dme/ap_romstage.c
+++ b/src/mainboard/supermicro/h8dme/ap_romstage.c
@@ -25,7 +25,7 @@
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
-#define SET_NB_CFG_54 1 
+#define SET_NB_CFG_54 1
 
 //used by raminit
 #define QRANK_DIMM_SUPPORT 1
diff --git a/src/mainboard/supermicro/h8dme/cmos.layout b/src/mainboard/supermicro/h8dme/cmos.layout
index 9d37e2bba6..518f9458b6 100644
--- a/src/mainboard/supermicro/h8dme/cmos.layout
+++ b/src/mainboard/supermicro/h8dme/cmos.layout
@@ -1,23 +1,23 @@
-## 
+##
 ## This file is part of the coreboot project.
-## 
+##
 ## Copyright (C) 2007 AMD
 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## 
+##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
 ## (at your option) any later version.
-## 
+##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
-## 
+##
 ## You should have received a copy of the GNU General Public License
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
+##
 
 entries
 
diff --git a/src/mainboard/supermicro/h8dme/devicetree.cb b/src/mainboard/supermicro/h8dme/devicetree.cb
index 5d6776a3f2..f6f75efb65 100644
--- a/src/mainboard/supermicro/h8dme/devicetree.cb
+++ b/src/mainboard/supermicro/h8dme/devicetree.cb
@@ -8,9 +8,9 @@ chip northbridge/amd/amdk8/root_complex
 		chip northbridge/amd/amdk8 #mc0
 			device pci 18.0 on end
 			device pci 18.0 on end
-			device pci 18.0 on 
-				#  devices on link 0, link 0 == LDT 0 
-			        chip southbridge/nvidia/mcp55 
+			device pci 18.0 on
+				#  devices on link 0, link 0 == LDT 0
+			        chip southbridge/nvidia/mcp55
 					device pci 0.0 on end   # HT
                 			device pci 1.0 on # LPC
 						chip superio/winbond/w83627hf
@@ -37,14 +37,14 @@ chip northbridge/amd/amdk8/root_complex
                 	                			irq 0x70 = 1
 								irq 0x72 = 12
 							end
-                	        			device pnp 2e.6 off  # SFI 
+                	        			device pnp 2e.6 off  # SFI
                 	                 			io 0x62 = 0x100
 							end
                 	        			device pnp 2e.7 off #  GPIO_GAME_MIDI
 								io 0x60 = 0x220
 								io 0x62 = 0x300
 								irq 0x70 = 9
-							end						
+							end
                 	        			device pnp 2e.8 off end #  WDTO_PLED
                 	        			device pnp 2e.9 off end #  GPIO_SUSLED
                 	        			device pnp 2e.a off end #  ACPI
@@ -67,24 +67,24 @@ chip northbridge/amd/amdk8/root_complex
 #                                                end
 #                                                chip drivers/generic/generic #PCIXB Slot1
 #                                                        device i2c 51 on end
-#                                                end     
+#                                                end
 #                                                chip drivers/generic/generic #PCIXB Slot2
 #                                                        device i2c 52 on end
-#                                                end             
+#                                                end
 #                                                chip drivers/generic/generic #PCI Slot1
 #                                                        device i2c 53 on end
-#                                                end              
+#                                                end
 #                                                chip drivers/generic/generic #Master MCP55 PCI-E
 #                                                        device i2c 54 on end
-#                                                end     
+#                                                end
 #                                                chip drivers/generic/generic #Slave MCP55 PCI-E
 #                                                        device i2c 55 on end
-#                                                end             
+#                                                end
                                                 chip drivers/generic/generic #MAC EEPROM
                                                         device i2c 51 on end
                                                 end
 
-                                        end # SM 
+                                        end # SM
 	                		device pci 2.0 on end # USB 1.1
         	        		device pci 2.1 on end # USB 2
                 			device pci 4.0 on end # IDE
@@ -116,15 +116,15 @@ chip northbridge/amd/amdk8/root_complex
 					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 					register "mac_eeprom_addr" = "0x51"
 				end
-			end #  device pci 18.0 
+			end #  device pci 18.0
 			device pci 18.1 on end
 			device pci 18.2 on end
 			device pci 18.3 on end
 		end # mc0
-		
+
 	end # PCI domain
-	
-#       chip drivers/generic/debug 
+
+#       chip drivers/generic/debug
 #               device pnp 0.0 off end # chip name
 #                device pnp 0.1 on end # pci_regs_all
 #                device pnp 0.2 off end # mem
@@ -135,5 +135,5 @@ chip northbridge/amd/amdk8/root_complex
 #                device pnp 0.7 off end # tsc
 #                device pnp 0.8 off  end # io
 #                device pnp 0.9 on end # io
-#       end  
+#       end
 end #root_complex
diff --git a/src/mainboard/supermicro/h8dme/get_bus_conf.c b/src/mainboard/supermicro/h8dme/get_bus_conf.c
index 3a9218ba6c..5052f35d7b 100644
--- a/src/mainboard/supermicro/h8dme/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8dme/get_bus_conf.c
@@ -40,7 +40,7 @@
 
 	unsigned char bus_pcix[3]; // under bus_mcp55_2
 
-unsigned pci1234x[] = 
+unsigned pci1234x[] =
 {        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
 	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
         0x0000ff0,
@@ -52,7 +52,7 @@ unsigned pci1234x[] =
 //        0x0000ff0,
 //        0x0000ff0
 };
-unsigned hcdnx[] = 
+unsigned hcdnx[] =
 { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
 	0x20202020,
 	0x20202020,
@@ -98,7 +98,7 @@ void get_bus_conf(void)
 	for(i=0; i<8; i++) {
 		bus_mcp55[i] = 0;
 	}
-	
+
 	for(i=0; i<3; i++) {
 		bus_pcix[i] = 0;
 	}
@@ -142,13 +142,13 @@ void get_bus_conf(void)
 	                        }
 			}
 		}
-		
+
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
 #if CONFIG_LOGICAL_CPUS==1
 	apicid_base = get_apicid_base(1);
-#else 
-	apicid_base = CONFIG_MAX_PHYSICAL_CPUS; 
+#else
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
 #endif
 	apicid_mcp55 = apicid_base+0;
 
diff --git a/src/mainboard/supermicro/h8dme/irq_tables.c b/src/mainboard/supermicro/h8dme/irq_tables.c
index 5cb6d8420c..bc6aded97f 100644
--- a/src/mainboard/supermicro/h8dme/irq_tables.c
+++ b/src/mainboard/supermicro/h8dme/irq_tables.c
@@ -19,7 +19,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* This file was generated by getpir.c, do not modify! 
+/* This file was generated by getpir.c, do not modify!
    (but if you do, please run checkpir on it to verify)
    Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
 
@@ -33,11 +33,11 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, 
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
 		uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
 		uint8_t slot, uint8_t rfu)
 {
-        pirq_info->bus = bus; 
+        pirq_info->bus = bus;
         pirq_info->devfn = devfn;
                 pirq_info->irq[0].link = link0;
                 pirq_info->irq[0].bitmap = bitmap0;
@@ -79,15 +79,15 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
-	
+
 	pirq->signature = PIRQ_SIGNATURE;
 	pirq->version  = PIRQ_VERSION;
-	
+
 	pirq->rtr_bus = bus_mcp55[0];
 	pirq->rtr_devfn = ((sbdn+6)<<3)|0;
 
 	pirq->exclusive_irqs = 0;
-	
+
 	pirq->rtr_vendor = 0x10de;
 	pirq->rtr_device = 0x0370;
 
@@ -100,11 +100,11 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 //pci bridge
 	write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 	pirq_info++; slot_num++;
-        
-	pirq->size = 32 + 16 * slot_num; 
+
+	pirq->size = 32 + 16 * slot_num;
 
         for (i = 0; i < pirq->size; i++)
-                sum += v[i];	
+                sum += v[i];
 
 	sum = pirq->checksum - sum;
 
diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c
index c7e46f2bda..8146923ef7 100644
--- a/src/mainboard/supermicro/h8dme/mptable.c
+++ b/src/mainboard/supermicro/h8dme/mptable.c
@@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v)
 
 
 	}
-  
+
 /*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
 */	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_mcp55, 0x1);
@@ -144,9 +144,9 @@ static void *smp_write_config_table(void *v)
         }
 
 
-	if(bus_pcix[0]) {	
+	if(bus_pcix[0]) {
 		for(i=0;i<2;i++) {
-			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17
 		}
 
 		for(i=0;i<4;i++) {
diff --git a/src/mainboard/supermicro/h8dme/resourcemap.c b/src/mainboard/supermicro/h8dme/resourcemap.c
index fa22ee337b..db5d5fe185 100644
--- a/src/mainboard/supermicro/h8dme/resourcemap.c
+++ b/src/mainboard/supermicro/h8dme/resourcemap.c
@@ -161,7 +161,7 @@ static void setup_mb_resource_map(void)
 		 *	   1 = base/limit registers i are read-only
 		 * [ 7: 4] Reserved
 		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-		 *	   This field defines the upper address bits of a 40bit address 
+		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
 		PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
@@ -217,7 +217,7 @@ static void setup_mb_resource_map(void)
 		 * [ 3: 2] Reserved
 		 * [ 4: 4] VGA Enable
 		 *	   0 = VGA matches Disabled
-		 *	   1 = matches all address < 64K and where A[9:0] is in the 
+		 *	   1 = matches all address < 64K and where A[9:0] is in the
 		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
 		 * [ 5: 5] ISA Enable
 		 *	   0 = ISA matches Disabled
@@ -225,7 +225,7 @@ static void setup_mb_resource_map(void)
 		 *	       from matching agains this base/limit pair
 		 * [11: 6] Reserved
 		 * [24:12] PCI I/O Base i
-		 *	   This field defines the start of PCI I/O region n 
+		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
 		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
@@ -270,9 +270,9 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the highest bus number in configuration region i
 		 */
 		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
-		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 
 	};