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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-24 00:04:22 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-31 03:41:11 +0000 |
commit | 1740230ace3aeede3a7ee5cadd1e17744cda07b3 (patch) | |
tree | bf4e9f45d71fef44056ba901ac91fcbfb423a525 /src/mainboard/supermicro/h8dme/get_bus_conf.c | |
parent | f054a4bf3d6ce459d15c9375e4ca2390d04ffb68 (diff) |
Remove all AMD K8 boards
Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.
Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/supermicro/h8dme/get_bus_conf.c')
-rw-r--r-- | src/mainboard/supermicro/h8dme/get_bus_conf.c | 145 |
1 files changed, 0 insertions, 145 deletions
diff --git a/src/mainboard/supermicro/h8dme/get_bus_conf.c b/src/mainboard/supermicro/h8dme/get_bus_conf.c deleted file mode 100644 index 8b8b2f9ea0..0000000000 --- a/src/mainboard/supermicro/h8dme/get_bus_conf.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu@amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <string.h> -#include <stdint.h> -#include <cpu/amd/multicore.h> - -#include <cpu/amd/amdk8_sysconf.h> -#include <stdlib.h> - -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -//busnum is default -unsigned char bus_mcp55[8]; //1 -unsigned apicid_mcp55; - -unsigned char bus_pcix[3]; // under bus_mcp55_2 - -unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, - 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 -}; - -unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most - 0x20202020, - 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -}; - -unsigned sbdnb; - -static unsigned get_bus_conf_done = 0; - -void get_bus_conf(void) -{ - - unsigned apicid_base; - unsigned sbdn; - - struct device *dev; - int i; - - if (get_bus_conf_done == 1) - return; //do it only once - - get_bus_conf_done = 1; - - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for (i = 0; i < sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } - - get_sblk_pci1234(); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain - sbdn = sysconf.sbdn; - - sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain - - for (i = 0; i < 8; i++) { - bus_mcp55[i] = 0; - } - - for (i = 0; i < 3; i++) { - bus_pcix[i] = 0; - } - - bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff; - - /* MCP55 */ - dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06, 0)); - if (dev) { - bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_mcp55[2]++; - } else { - printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x06); - - bus_mcp55[1] = 2; - bus_mcp55[2] = 3; - } - - for (i = 2; i < 8; i++) { - dev = - dev_find_slot(bus_mcp55[0], - PCI_DEVFN(sbdn + 0x0a + i - 2, 0)); - if (dev) { - bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - bus_mcp55[0], sbdn + 0x0a + i - 2); - } - } - - if (bus_mcp55[2]) { - for (i = 0; i < 2; i++) { - dev = dev_find_slot(bus_mcp55[2], PCI_DEVFN(0, i)); - if (dev) { - bus_pcix[0] = bus_mcp55[2]; - bus_pcix[i + 1] = - pci_read_config8(dev, PCI_SECONDARY_BUS); - } - } - } - -/*I/O APICs: APIC ID Version State Address*/ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_mcp55 = apicid_base + 0; - -} |