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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-24 00:04:22 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-31 03:41:11 +0000 |
commit | 1740230ace3aeede3a7ee5cadd1e17744cda07b3 (patch) | |
tree | bf4e9f45d71fef44056ba901ac91fcbfb423a525 /src/mainboard/sunw/ultra40m2/Kconfig | |
parent | f054a4bf3d6ce459d15c9375e4ca2390d04ffb68 (diff) |
Remove all AMD K8 boards
Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.
Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/sunw/ultra40m2/Kconfig')
-rw-r--r-- | src/mainboard/sunw/ultra40m2/Kconfig | 79 |
1 files changed, 0 insertions, 79 deletions
diff --git a/src/mainboard/sunw/ultra40m2/Kconfig b/src/mainboard/sunw/ultra40m2/Kconfig deleted file mode 100644 index 2913ae8c30..0000000000 --- a/src/mainboard/sunw/ultra40m2/Kconfig +++ /dev/null @@ -1,79 +0,0 @@ -if BOARD_SUNW_ULTRA40M2 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_SOCKET_F - select DIMM_DDR2 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDK8 - select SOUTHBRIDGE_NVIDIA_MCP55 - select HT_CHAIN_DISTRIBUTE - select MCP55_USE_NIC - select MCP55_USE_AZA - select SUPERIO_SMSC_DME1737 - select PARALLEL_CPU_INIT - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select LIFT_BSP_APIC_ID - select BOARD_ROMSIZE_KB_1024 - select QRANK_DIMM_SUPPORT - select K8_ALLOCATE_IO_RANGE - -config MAINBOARD_DIR - string - default sunw/ultra40m2 - -config DCACHE_RAM_BASE - hex - default 0xc8000 - -config DCACHE_RAM_SIZE - hex - default 0x08000 - -config APIC_ID_OFFSET - hex - default 0x10 - -config MEM_TRAIN_SEQ - int - default 1 - -config MCP55_NUM - int - default 2 - -config MAINBOARD_PART_NUMBER - string - default "Ultra 40 M2" - -config MAX_CPUS - int - default 4 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x20 - -config IRQ_SLOT_COUNT - int - default 11 - -config MCP55_PCI_E_X_0 - int - default 1 - -config MCP55_PCI_E_X_1 - int - default 1 - -endif # BOARD_SUNW_ULTRA40M2 |