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authorMyles Watson <mylesgw@gmail.com>2009-11-06 23:42:26 +0000
committerMyles Watson <mylesgw@gmail.com>2009-11-06 23:42:26 +0000
commitd27c08c2898d1d74765a7799628d1c18369fd671 (patch)
tree7ac357d2b44d833c6efe70d1e691c6611c521e8d /src/mainboard/sunw/ultra40
parent547d48ab01049a634dccb16d1847524d5ba93e33 (diff)
Remove drivers/pci/onboard. The only purpose was for option ROMs, which are
now handled more generically using CBFS. Simplify the option ROM code in device/pci_rom.c, since there are only two ways to get a ROM address now (CBFS and the device) and add an exception for qemu. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/sunw/ultra40')
-rw-r--r--src/mainboard/sunw/ultra40/Config.lb3
-rw-r--r--src/mainboard/sunw/ultra40/devicetree.cb3
2 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/sunw/ultra40/Config.lb b/src/mainboard/sunw/ultra40/Config.lb
index 6fedd3a7ed..b00c2bc331 100644
--- a/src/mainboard/sunw/ultra40/Config.lb
+++ b/src/mainboard/sunw/ultra40/Config.lb
@@ -210,8 +210,6 @@ chip northbridge/amd/amdk8/root_complex
register "ide1_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
-# register "nic_rom_address" = "0xfff80000" # 64k
-# register "raid_rom_address" = "0xfff90000"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51"
end
@@ -243,7 +241,6 @@ chip northbridge/amd/amdk8/root_complex
device pci c.0 off end # PCI E 2
device pci d.0 off end # PCI E 1
device pci e.0 on end # PCI E 0
-# register "nic_rom_address" = "0xfff80000" # 64k
register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51"
end
diff --git a/src/mainboard/sunw/ultra40/devicetree.cb b/src/mainboard/sunw/ultra40/devicetree.cb
index 01a59f714e..afa6f66beb 100644
--- a/src/mainboard/sunw/ultra40/devicetree.cb
+++ b/src/mainboard/sunw/ultra40/devicetree.cb
@@ -106,8 +106,6 @@ chip northbridge/amd/amdk8/root_complex
register "ide1_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
-# register "nic_rom_address" = "0xfff80000" # 64k
-# register "raid_rom_address" = "0xfff90000"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51"
end
@@ -139,7 +137,6 @@ chip northbridge/amd/amdk8/root_complex
device pci c.0 off end # PCI E 2
device pci d.0 off end # PCI E 1
device pci e.0 on end # PCI E 0
-# register "nic_rom_address" = "0xfff80000" # 64k
register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51"
end