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authorSubrata Banik <subratabanik@google.com>2022-03-10 17:53:14 +0530
committerSubrata Banik <subratabanik@google.com>2022-03-15 10:17:25 +0000
commit2eb51aace5489b2f2d20e510f19a1e3b17bf1d60 (patch)
tree9bf2dcdc8ca37ca5aa4c49a24c0c5e764928d7f1 /src/mainboard/starlabs
parent5730d018d1395cf68c2fe0e795831f6780c734de (diff)
{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype
This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Diffstat (limited to 'src/mainboard/starlabs')
-rw-r--r--src/mainboard/starlabs/labtop/variants/tgl/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/romstage.c b/src/mainboard/starlabs/labtop/variants/tgl/romstage.c
index 1d65c61ba5..fed6efc9e4 100644
--- a/src/mainboard/starlabs/labtop/variants/tgl/romstage.c
+++ b/src/mainboard/starlabs/labtop/variants/tgl/romstage.c
@@ -25,7 +25,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
},
};
- memcfg_init(&mupd->FspmConfig, &mem_config, &ddr4_spd_info, half_populated);
+ memcfg_init(mupd, &mem_config, &ddr4_spd_info, half_populated);
const uint8_t vtd = get_uint_option("vtd", 1);
mupd->FspmConfig.VtdDisable = !vtd;