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authorSean Rhodes <sean@starlabs.systems>2022-06-06 08:38:49 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-06-20 12:02:53 +0000
commitb7c1a3aee930aa6811cac94bdd57dcaa0e824752 (patch)
tree544fec1181a3a3c0e32782331201e322532bc085 /src/mainboard/starlabs
parent7a82a805b8b33d97e5208ed74ecf33803f07c736 (diff)
mb/starlabs/lite/glkr: Configure LPC IO registers
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2d949af0086c231e27ac889c0aabd0d3e00c94fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/starlabs')
-rw-r--r--src/mainboard/starlabs/lite/variants/glkr/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
index 7bbeea7a9f..5cfcb4033d 100644
--- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
+++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
@@ -127,6 +127,9 @@ chip soc/intel/apollolake
device pci 1c.0 off end # eMMC
device pci 1e.0 off end # SDIO
device pci 1f.0 on # LPC Interface
+ register "gen1_dec" = "0x000c06a1"
+ register "gen2_dec" = "0x000c0081"
+
chip ec/starlabs/merlin
# Port pair 4Eh/4Fh
device pnp 4e.00 on end # IO Interface