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authorNico Huber <nico.h@gmx.de>2024-01-12 16:22:19 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-02-19 13:19:26 +0000
commit2bc4b934c35ca14ab1243c19dc6fa27688feefdb (patch)
tree616e44e74f59f63376dbd7f3b5febbd31d02262c /src/mainboard/starlabs
parent3d80d14cd4ed82e74057cea884dcb9bb7588c076 (diff)
soc/intel/tigerlake: Drop redundant PcieRpEnable
The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79920 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/starlabs')
-rw-r--r--src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
index b870ec1410..2b7c4f8f8d 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
@@ -133,7 +133,6 @@ chip soc/intel/tigerlake
device ref uart2 on end
device ref pcie_rp9 on
register "HybridStorageMode" = "0"
- register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[3]" = "0x08"
register "PcieClkSrcClkReq[3]" = "3"