diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2024-10-04 13:20:48 +0100 |
|---|---|---|
| committer | Sean Rhodes <sean@starlabs.systems> | 2024-10-11 11:27:42 +0000 |
| commit | 5072fb19644cfaaa4d39144b2e5ca7b7c899c0f2 (patch) | |
| tree | 1852084b9dfdefc2138b9bfbca8e72f511ea9691 /src/mainboard/starlabs/starlite_adl | |
| parent | 9820363f5fbb6166d5d84543eb3038b643301168 (diff) | |
mb/starlabs/*: Rework the performance profiles
Rather than hardcoded values, simply change these to -25% of the
defaults for Power Saving, and +25% for Performance.
Change-Id: I16aeb4d5dc25a3f240a775509276c9d3189e9699
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84661
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/starlabs/starlite_adl')
| -rw-r--r-- | src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c index 075cc70e47..8c35c5ce24 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c @@ -23,25 +23,27 @@ void devtree_update(void) struct device *touchscreen_dev = pcidev_on_root(0x15, 2); struct device *accelerometer_dev = pcidev_on_root(0x15, 0); + uint8_t performance_scale = 100; + /* Update PL1 & PL2 based on CMOS settings */ switch (get_power_profile(PP_POWER_SAVER)) { case PP_POWER_SAVER: - soc_conf_4core->tdp_pl1_override = 6; - soc_conf_4core->tdp_pl2_override = 10; + performance_scale -= 25; common_config->pch_thermal_trip = 30; break; case PP_BALANCED: - soc_conf_4core->tdp_pl1_override = 10; - soc_conf_4core->tdp_pl2_override = 25; + /* Use the Intel defaults */ common_config->pch_thermal_trip = 25; break; case PP_PERFORMANCE: - soc_conf_4core->tdp_pl1_override = 20; - soc_conf_4core->tdp_pl2_override = 35; + performance_scale += 25; common_config->pch_thermal_trip = 20; break; } + soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl1_override * performance_scale) / 100; + soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100; + /* Set PL4 to 1.0C */ soc_conf_4core->tdp_pl4 = 37; |