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authorSean Rhodes <sean@starlabs.systems>2024-09-09 12:43:39 +0100
committerSean Rhodes <sean@starlabs.systems>2024-10-03 09:34:38 +0000
commit74d4530f4ad532d9270534559b8d10218bbe62dc (patch)
tree8af9b4ef4ac5b4b2384d5937cbeea395cdf51152 /src/mainboard/starlabs/starbook/variants
parent55e265ea39506d2b340e5c6d621b42ac61d33702 (diff)
mb/starlabs/starbook/tgl: Remove PMC GPIO routing
These aren't used so remove them. Change-Id: I6fd33c5242adb93b1251af9c5b11be3734a7aceb Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/starlabs/starbook/variants')
-rw-r--r--src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb10
1 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
index 3f7762120e..aa9db2a7c4 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
@@ -33,16 +33,6 @@ chip soc/intel/tigerlake
register "PchPmSlpSusMinAssert" = "3" # 500ms
register "PchPmSlpAMinAssert" = "3" # 2s
- # PM Util
- # GPE configuration
- # Note that GPE events called out in ASL code rely on this
- # route. i.e. If this route changes then the affected GPE
- # offset bits also need to be changed.
- # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
- register "pmc_gpe0_dw0" = "GPP_B"
- register "pmc_gpe0_dw1" = "GPP_C"
- register "pmc_gpe0_dw2" = "GPP_E"
-
# Enable the correct decode ranges on the LPC bus.
register "lpc_ioe" = "LPC_IOE_EC_4E_4F |
LPC_IOE_SUPERIO_2E_2F |