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authorSean Rhodes <sean@starlabs.systems>2024-09-09 12:43:02 +0100
committerSean Rhodes <sean@starlabs.systems>2024-10-03 09:34:31 +0000
commit55e265ea39506d2b340e5c6d621b42ac61d33702 (patch)
tree3447f7244ed3b71de414570a1c1e387a32ef230c /src/mainboard/starlabs/starbook/variants
parent627468f12ec1e61a5439652922c0ce2aa8b66ccf (diff)
mb/starlabs/starbook/tgl: Alphabetize and group FSP UPDs
Change-Id: I6bab0a316ea7d0f7dfbf599e5c08517cee559635 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/starlabs/starbook/variants')
-rw-r--r--src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb14
1 files changed, 5 insertions, 9 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
index 11441621c2..3f7762120e 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
@@ -1,7 +1,10 @@
chip soc/intel/tigerlake
-# CPU
- # Enable Enhanced Intel SpeedStep
+ # FSP UPDs
register "eist_enable" = "true"
+ register "enable_c6dram" = "1"
+ register "CnviBtCore" = "true"
+ register "CnviBtAudioOffload" = "1"
+ register "SaGv" = "SaGv_Enabled"
# Graphics
# Not used but timings left for reference
@@ -14,13 +17,6 @@ chip soc/intel/tigerlake
# .backlight_pwm_hz = 200, // PWM
# }"
- # FSP Memory
- register "CnviBtCore" = "true"
- register "CnviBtAudioOffload" = "1"
- register "enable_c6dram" = "1"
- register "SaGv" = "SaGv_Enabled"
-
- # FSP Silicon
# Serial I/O
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,