diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2023-05-31 14:36:22 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-06-02 17:58:46 +0000 |
| commit | 7e5b28feb6a0b14c4303b9610bee3277dd8077fe (patch) | |
| tree | 9045f9d524e05113c8b58b2264651651e40bf2b0 /src/mainboard/starlabs/lite | |
| parent | 923215184d3720d836c2be75a95c629af6dac7c9 (diff) | |
soc/intel/apollolake: Switch to snake case for SataPortsEnable
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'SataPortsEnable'.
Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Diffstat (limited to 'src/mainboard/starlabs/lite')
| -rw-r--r-- | src/mainboard/starlabs/lite/variants/glk/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/starlabs/lite/variants/glkr/devicetree.cb | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index f1ace5a559..fb9070fd34 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -71,7 +71,7 @@ chip soc/intel/apollolake device ref heci2 on end device ref heci3 on end device ref sata on - register "SataPortsEnable[0]" = "1" + register "sata_ports_enable[0]" = "1" end device ref xhci on # Motherboard USB Type C diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index 71932a6450..b4e627c4ab 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -71,7 +71,7 @@ chip soc/intel/apollolake device ref heci2 on end device ref heci3 on end device ref sata on - register "SataPortsEnable[0]" = "1" + register "sata_ports_enable[0]" = "1" end device ref xhci on # Motherboard USB Type C |