summaryrefslogtreecommitdiff
path: root/src/mainboard/starlabs/labtop
diff options
context:
space:
mode:
authorSean Rhodes <sean@starlabs.systems>2022-05-26 21:04:10 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-06-20 12:15:52 +0000
commit99d2d62fa1034ac3935dd701735704ca839c25a1 (patch)
treece474cfbee6ee23701272da589fd4dee87c369e0 /src/mainboard/starlabs/labtop
parent49d0204c31a50c5b470d5c65781790b378c5f903 (diff)
mb/starlabs/labtop: Configure tcc_offset based on power_profile settings
Set tcc_offset value based on the power_profile value, ranging from 10 to 20 degrees. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I66fb266c1730833ff6e2dbf8ea39f23ee0878590 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/starlabs/labtop')
-rw-r--r--src/mainboard/starlabs/labtop/variants/cml/devicetree.cb3
-rw-r--r--src/mainboard/starlabs/labtop/variants/cml/devtree.c25
-rw-r--r--src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb3
-rw-r--r--src/mainboard/starlabs/labtop/variants/tgl/devtree.c27
4 files changed, 29 insertions, 29 deletions
diff --git a/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb
index 3bf0d7a74b..74125488f8 100644
--- a/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb
+++ b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb
@@ -32,9 +32,6 @@ chip soc/intel/cannonlake
register "PchPmSlpSusMinAssert" = "3" # 500ms
register "PchPmSlpAMinAssert" = "3" # 2s
- # Thermal
- register "tcc_offset" = "10"
-
# PM Util
# GPE configuration
# Note that GPE events called out in ASL code rely on this
diff --git a/src/mainboard/starlabs/labtop/variants/cml/devtree.c b/src/mainboard/starlabs/labtop/variants/cml/devtree.c
index cf0734e4ce..93d55c58ae 100644
--- a/src/mainboard/starlabs/labtop/variants/cml/devtree.c
+++ b/src/mainboard/starlabs/labtop/variants/cml/devtree.c
@@ -17,19 +17,22 @@ void devtree_update(void)
struct device *nic_dev = pcidev_on_root(0x14, 3);
/* Update PL1 & PL2 based on CMOS settings */
- switch (get_uint_option("power_profile", 0)) {
- case 1:
- soc_conf->tdp_pl1_override = 17;
- soc_conf->tdp_pl2_override = 20;
+ switch (get_power_profile(PP_POWER_SAVER)) {
+ case PP_POWER_SAVER:
+ disable_turbo();
+ soc_conf->tdp_pl1_override = 15;
+ soc_conf->tdp_pl2_override = 15;
+ cfg->tcc_offset = 20;
break;
- case 2:
- soc_conf->tdp_pl1_override = 20;
- soc_conf->tdp_pl2_override = 25;
+ case PP_BALANCED:
+ soc_conf->tdp_pl1_override = 17;
+ soc_conf->tdp_pl2_override = 20;
+ cfg->tcc_offset = 15;
break;
- default:
- disable_turbo();
- soc_conf->tdp_pl1_override = 15;
- soc_conf->tdp_pl2_override = 15;
+ case PP_PERFORMANCE:
+ soc_conf->tdp_pl1_override = 20;
+ soc_conf->tdp_pl2_override = 25;
+ cfg->tcc_offset = 10;
break;
}
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
index ed65f4e11a..af6ba24599 100644
--- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
@@ -38,9 +38,6 @@ chip soc/intel/tigerlake
register "PchPmSlpSusMinAssert" = "3" # 500ms
register "PchPmSlpAMinAssert" = "3" # 2s
- # Thermal
- register "tcc_offset" = "10"
-
# PM Util
# GPE configuration
# Note that GPE events called out in ASL code rely on this
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devtree.c b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c
index 09d26e8ecc..51243da7a6 100644
--- a/src/mainboard/starlabs/labtop/variants/tgl/devtree.c
+++ b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c
@@ -27,22 +27,25 @@ void devtree_update(void)
switch (get_power_profile(PP_POWER_SAVER)) {
case PP_POWER_SAVER:
disable_turbo();
- soc_conf_2core->tdp_pl1_override = 15;
- soc_conf_4core->tdp_pl1_override = 15;
- soc_conf_2core->tdp_pl2_override = 15;
- soc_conf_4core->tdp_pl2_override = 15;
+ soc_conf_2core->tdp_pl1_override = 15;
+ soc_conf_4core->tdp_pl1_override = 15;
+ soc_conf_2core->tdp_pl2_override = 15;
+ soc_conf_4core->tdp_pl2_override = 15;
+ cfg->tcc_offset = 20;
break;
case PP_BALANCED:
- soc_conf_2core->tdp_pl1_override = 15;
- soc_conf_4core->tdp_pl1_override = 15;
- soc_conf_2core->tdp_pl2_override = 25;
- soc_conf_4core->tdp_pl2_override = 25;
+ soc_conf_2core->tdp_pl1_override = 15;
+ soc_conf_4core->tdp_pl1_override = 15;
+ soc_conf_2core->tdp_pl2_override = 25;
+ soc_conf_4core->tdp_pl2_override = 25;
+ cfg->tcc_offset = 15;
break;
case PP_PERFORMANCE:
- soc_conf_2core->tdp_pl1_override = 28;
- soc_conf_4core->tdp_pl1_override = 28;
- soc_conf_2core->tdp_pl2_override = 40;
- soc_conf_4core->tdp_pl2_override = 40;
+ soc_conf_2core->tdp_pl1_override = 28;
+ soc_conf_4core->tdp_pl1_override = 28;
+ soc_conf_2core->tdp_pl2_override = 40;
+ soc_conf_4core->tdp_pl2_override = 40;
+ cfg->tcc_offset = 10;
break;
}