diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2022-01-04 11:09:41 +0000 |
|---|---|---|
| committer | Martin Roth - Personal <martinroth@google.com> | 2022-02-22 19:21:22 +0000 |
| commit | 70a1ef071693af72061f5eef1ee24e56712c55a1 (patch) | |
| tree | 5ad84a49e0a53b4056f1f38cbc475619430eeab0 /src/mainboard/starlabs/labtop | |
| parent | ad58a188e84ff4aa90c6ea6b42c0d93858e17c66 (diff) | |
mb/starlabs/labtop: Reconfigure CNVi GPIOs
Reconfigure the CNVi GPIO's so that they are configured correctly.
The original configuration was based on the AMI firmware, and
whilst it worked, it wasn't optimal.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9fc9963e91da0267c8740fee20a3ec41895b4953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/starlabs/labtop')
| -rw-r--r-- | src/mainboard/starlabs/labtop/variants/tgl/gpio.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c index 81de01e325..559de8d4d3 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c +++ b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c @@ -279,15 +279,15 @@ const struct pad_config gpio_table[] = { /* F0: CNV_BRI_DT_BT_UART0_RTS_R */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* F1: CNV_BRI_RSP_BT_UART0_RX_R */ - PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* F2: CNV_RGI_DT_BT_UART0_TX_R */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* F3: CNV_RGI_RSP_BT_UART0_CTS */ - PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* F4: Not Connected */ PAD_NC(GPP_F4, NONE), /* F5: GPPC_F5_MODEM_CLKREQ */ - PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + PAD_NC(GPP_F5, NONE), /* F6: Not Connected */ PAD_NC(GPP_F6, NONE), /* F7: BIOS_REC */ |