src/mainboard: Add Star Labs labtop series

Add support for LabTop Mk III (kblr) and LabTop Mk IV (cml)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

19 files changed, 1306 insertions, 0 deletions

diff --git a/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h
new file mode 100644
index 0000000000..47e2688a56
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MEMORY_H
+#define MEMORY_H
+
+u8 get_memory_config_straps(void);
+const struct cnl_mb_cfg *get_memory_cfg(struct cnl_mb_cfg *mem_cfg);
+
+#endif
diff --git a/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h
new file mode 100644
index 0000000000..cfcc6ab08d
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_ROMSTAGE_H
+#define VARIANT_ROMSTAGE_H
+
+void variant_configure_fspm(FSPM_UPD *memupd);
+
+#endif
diff --git a/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000000..454749ff3a
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _BASEBOARD_VARIANTS_H_
+#define _BASEBOARD_VARIANTS_H_
+
+#include <soc/gpio.h>
+
+/*
+ * The next set of functions return the gpio table and fill in the number of
+ * entries for each table.
+ */
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+
+#endif /* _BASEBOARD_VARIANTS_H_ */
diff --git a/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc b/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc
new file mode 100644
index 0000000000..79b824bef7
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += romstage.c
diff --git a/src/mainboard/starlabs/labtop/variants/cml/board.fmd b/src/mainboard/starlabs/labtop/variants/cml/board.fmd
new file mode 100644
index 0000000000..9018104edd
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/board.fmd
@@ -0,0 +1,14 @@
+#
+# Manually defined FMD in order to ensure that space is reserved for the EC
+# at the top of the BIOS region.
+#
+FLASH 16M {
+	BIOS@0x400000 0xC00000 {
+		EC@0x0 0x20000
+		RW_MRC_CACHE@0x20000 0x10000
+		SMMSTORE@0x30000 0x40000
+		CONSOLE@0x70000 0x20000
+		FMAP@0x90000 0x200
+		COREBOOT(CBFS)
+	}
+}
diff --git a/src/mainboard/starlabs/labtop/variants/cml/data.vbt b/src/mainboard/starlabs/labtop/variants/cml/data.vbt
new file mode 100644
index 0000000000..bae92100eb
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/data.vbt
diff --git a/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb
new file mode 100644
index 0000000000..a6773f1e12
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb
@@ -0,0 +1,186 @@
+chip soc/intel/cannonlake
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		 /* Touchpad */
+		 .i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		 },
+	}"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	# Power limit
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 20,
+	}"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# Graphics (soc/intel/cannonlake/graphics.c)
+	# IGD Displays
+	register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	# FSP configuration
+	register "SaGv" = "SaGv_Enabled"
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
+	}"
+
+	# Misc
+	register "AcousticNoiseMitigation" = "1"
+
+	# Power
+	register "PchPmSlpS3MinAssert" = "2"		# 50ms
+	register "PchPmSlpS4MinAssert" = "3"		# 1s
+	register "PchPmSlpSusMinAssert" = "3"		# 500ms
+	register "PchPmSlpAMinAssert" = "3"		# 2s
+
+	# Thermal
+	register "tcc_offset" = "10"
+
+	# Enable eDP device
+	# register "DdiPortEdp" = "1"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "gpe0_dw0" = "PMC_GPP_B"
+	register "gpe0_dw1" = "PMC_GPP_C"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree.
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on  end				# Host Bridge
+		device pci 02.0 on  end				# Integrated Graphics Device
+		device pci 04.0 on				# SA Thermal Device
+			register "Device4Enable" = "1"
+		end
+		device pci 12.0 on  end				# Thermal Subsystem
+		device pci 12.5 off end				# UFS SCS
+		device pci 12.6 off end				# GSPI #2
+		device pci 14.0 on				# USB xHCI
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC2)"		# Type-C Port 1
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port 2
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC2)"		# Bluetooth
+			register "usb2_ports[3]" = "USB2_PORT_MID(OC2)"		# SD Card
+			register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"		# Type-A Port 3
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC3)"		# Camera
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# CNVi Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"
+		end
+		device pci 14.1 off end				# USB xDCI (OTG)
+		device pci 14.3 on				# CNVi wifi
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device pci 14.5 off end				# SDCard
+		device pci 15.0 on				# I2C #0
+			chip drivers/i2c/hid
+				register "generic.hid" = ""StarPoint""
+				register "generic.desc" = ""Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end
+		device pci 15.1 off end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on	# SATA
+			register "SataSalpSupport" = "1"
+			# Port 1
+			register "SataPortsEnable[1]" = "1"
+			register "SataPortsDevSlp[1]" = "1"
+			# Port 2
+			register "SataPortsEnable[2]" = "1"
+			register "SataPortsDevSlp[2]" = "1"
+		end
+		device pci 19.0 off end				# I2C #4
+		device pci 19.1 off end				# I2C #5
+		device pci 19.2 on  end				# UART #2
+		device pci 1a.0 off end				# eMMC - not fitted
+		device pci 1c.0 off end				# PCI Express Port 1
+		device pci 1c.1 off end				# PCI Express Port 2
+		device pci 1c.2 off end				# PCI Express Port 3
+		device pci 1c.3 off end				# PCI Express Port 4
+		device pci 1c.4 off end				# PCI Express Port 5
+		device pci 1c.5 off end				# PCI Express Port 6
+		device pci 1c.6 off end				# PCI Express Port 7
+		device pci 1c.7 off end				# PCI Express Port 8
+		device pci 1d.0 on				# PCI Express Port 9  (SSD x4)
+			device pci 00.0 on end
+			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieClkSrcUsage[1]" = "8"
+			register "PcieClkSrcClkReq[1]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
+		end
+		device pci 1d.1 off end				# PCI Express Port 10
+		device pci 1d.2 off end				# PCI Express Port 11
+		device pci 1d.3 off end				# PCI Express Port 12
+		device pci 1d.4 off end				# PCI Express Port 13 (LAN)
+		device pci 1d.5 off end				# PCI Express Port 14 (WLAN)
+		device pci 1d.6 off end # PCI Express Port 15
+		device pci 1d.7 off end # PCI Express Port 16
+		device pci 1e.0 on  end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on				# LPC Interface
+			# LPC configuration from lspci -s 1f.0 -xxx
+			# Address 0x84: Decode 0x680 - 0x68F
+			register "gen1_dec" = "0x000c0681"
+			# Address 0x88: Decode
+			register "gen2_dec" = "0x000c1641"
+			# Address 0x8C: Decode 0x200 - 0x2FF
+			register "gen3_dec" = "0x00fc0201"
+			# Address 0x90: Decode 0x80 - 0x8F (Port 80)
+			register "gen4_dec" = "0x000c0081"
+
+			chip ec/starlabs/it8987
+				# Port 4Eh/4Fh
+				device pnp 4e.0 on		# IO Interface
+				end
+			end
+		end
+		device pci 1f.1 off end				# P2SB
+		device pci 1f.2 on end				# Power Management Controller
+		device pci 1f.3 on				# Intel HDA
+			subsystemid 0x10ec 0x119e
+			register "PchHdaAudioLinkHda" = "1"
+		end
+		device pci 1f.4 on  end				# SMBus
+		device pci 1f.5 on  end				# PCH SPI
+		device pci 1f.6 off end				# GbE
+	end
+end
diff --git a/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads b/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads
new file mode 100644
index 0000000000..8402b39a94
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads
@@ -0,0 +1,18 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1,   -- USB-C
+      HDMI1, -- USB-C
+      HDMI2, -- HDMI
+      eDP,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h b/src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h
new file mode 100644
index 0000000000..a20be3122b
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h
@@ -0,0 +1,225 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _VARIANT_GPIO_H_
+#define _VARIANT_GPIO_H_
+
+#include "baseboard/variants.h"
+
+#ifndef __ACPI__
+
+/*
+ * All definitions are taken from a comparison of the output of "inteltool -a"
+ * using the stock BIOS and with coreboot.
+ */
+
+/* Early pad configuration in romstage.c */
+const struct pad_config early_gpio_table[] = {
+	PAD_CFG_GPO(GPP_E22, 1, PLTRST),
+	PAD_CFG_GPO(GPP_E23, 1, PLTRST),
+	PAD_CFG_GPI(GPP_H6, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_H7, NONE, PLTRST),
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Pad configuration in ramstage.c */
+const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPD0, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD7, 0, PWROK),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_A7, 0x40100100, 0x3000),
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1),
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST),
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_A15, 1, PLTRST),
+	PAD_CFG_TERM_GPO(GPP_A16, 1, UP_20K, PLTRST),
+	PAD_NC(GPP_A17, NONE),
+	PAD_NC(GPP_A18, UP_20K),
+	PAD_NC(GPP_A19, UP_20K),
+	PAD_NC(GPP_A20, UP_20K),
+	PAD_NC(GPP_A21, UP_20K),
+	PAD_NC(GPP_A22, UP_20K),
+	PAD_NC(GPP_A23, UP_20K),
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0000),
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B11, 1, PLTRST),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
+	PAD_CFG_TERM_GPO(GPP_B15, 1, UP_20K, PLTRST),
+	_PAD_CFG_STRUCT(GPP_B16, 0x80100100, 0x0000),
+	PAD_CFG_GPO(GPP_B17, 1, PLTRST),
+	PAD_CFG_GPO(GPP_B18, 0, DEEP),
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_CFG_GPO(GPP_B22, 0, DEEP),
+	PAD_CFG_GPO(GPP_B23, 1, DEEP),
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C2, 1, DEEP),
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_C5, 0x40880100, 0x0000),
+	PAD_NC(GPP_C6, NONE),
+	PAD_NC(GPP_C7, NONE),
+	_PAD_CFG_STRUCT(GPP_C8, 0x80100100, 0x3000),
+	_PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000),
+	PAD_CFG_GPO(GPP_C10, 0, PLTRST),
+	_PAD_CFG_STRUCT(GPP_C11, 0x40100100, 0x0000),
+	PAD_CFG_GPO(GPP_C12, 1, PLTRST),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_CFG_GPO(GPP_C15, 1, PLTRST),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_NC(GPP_C20, NONE),
+	PAD_NC(GPP_C21, NONE),
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_CFG_GPO(GPP_D9, 1, PLTRST),
+	_PAD_CFG_STRUCT(GPP_D10, 0x80100100, 0x0000),
+	_PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000),
+	PAD_CFG_GPO(GPP_D12, 0, DEEP),
+	PAD_NC(GPP_D13, NONE),
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D15, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D16, 0, PWROK),
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+	PAD_NC(GPP_D21, NONE),
+	PAD_NC(GPP_D22, NONE),
+	PAD_NC(GPP_D23, NONE),
+	PAD_NC(GPP_E0, NONE),
+	PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
+	PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST),
+	_PAD_CFG_STRUCT(GPP_E3, 0x82040100, 0x0000),
+	_PAD_CFG_STRUCT(GPP_E4, 0x80880100, 0x3000),
+	PAD_NC(GPP_E5, NONE),
+	PAD_NC(GPP_E6, NONE),
+	PAD_CFG_GPI(GPP_E7, NONE, PLTRST),
+	PAD_NC(GPP_E8, NONE),
+	_PAD_CFG_STRUCT(GPP_E9, 0x44001700, 0x0000),
+	_PAD_CFG_STRUCT(GPP_E10, 0x44001700, 0x0000),
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E15, 1, PLTRST),
+	_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x3000),
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_F0, 0x00000301, 0x0000),
+	PAD_CFG_GPO(GPP_F1, 0, PWROK),
+	PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST),
+	_PAD_CFG_STRUCT(GPP_F3, 0x84000300, 0x3000),
+	PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
+	PAD_NC(GPP_F8, NONE),
+	PAD_NC(GPP_F9, NONE),
+	PAD_CFG_GPI(GPP_F10, UP_20K, PLTRST),
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1),
+	PAD_NC(GPP_G0, NONE),
+	PAD_NC(GPP_G1, NONE),
+	PAD_NC(GPP_G2, NONE),
+	PAD_NC(GPP_G3, NONE),
+	PAD_NC(GPP_G4, NONE),
+	PAD_NC(GPP_G5, UP_20K),
+	PAD_NC(GPP_G6, NONE),
+	PAD_NC(GPP_G7, DN_20K),
+	PAD_NC(GPP_H0, UP_20K),
+	PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3),
+	PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3),
+	PAD_NC(GPP_H3, UP_20K),
+	PAD_NC(GPP_H4, NONE),
+	PAD_NC(GPP_H5, NONE),
+	PAD_NC(GPP_H8, NONE),
+	PAD_NC(GPP_H9, NONE),
+	PAD_CFG_GPO(GPP_H10, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H11, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H12, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H13, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H14, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H15, 1, PLTRST),
+	PAD_NC(GPP_H16, NONE),
+	PAD_CFG_GPO(GPP_H17, 0, DEEP),
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_H19, 1, PLTRST),
+	_PAD_CFG_STRUCT(GPP_H20, 0x84000300, 0x0000),
+	PAD_CFG_GPO(GPP_H21, 0, DEEP),
+	PAD_CFG_GPO(GPP_H22, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H23, 0, DEEP),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+#endif
+
+#endif
diff --git a/src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h b/src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h
new file mode 100644
index 0000000000..190474f6d1
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _HDA_VERB_H_
+#define _HDA_VERB_H_
+
+#include <device/azalia_device.h>
+#include <device/azalia.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0256,	// Codec Vendor / Device ID: Realtek ALC256
+	0xffffffff,	// Subsystem ID
+	0x0000002b,	// Number of jacks (NID entries)
+
+	/* Rest Codec First */
+	AZALIA_RESET(0x1),
+
+	/* HDA Codec Subsystem ID Verb-table
+	 HDA Codec Subsystem ID: 0x10EC119E */
+	0x0017209E,
+	0x00172111,
+	0x001722EC,
+	0x00172310,
+	/* Pin Widget Verb-table */
+	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a61120),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90171110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x02ab1020),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x022b1010),
+	/* ONE DOES NOT SIMPLY
+	   MAKE IT WORK WITH WINDOWS */
+	/* RESET to D0 */
+	0x00170500,
+	0x00170500,
+	0x00170500,
+	0x00170500,
+	/* RESET Register */
+	0x0205001A,
+	0x02048003,
+	0x0205001A,
+	0x0204C003,
+	/* ALC256 default-1(Class D RESET) */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+	/* ALC256 default-2 */
+	0x02050040,
+	0x02049800,
+	0x02050034,
+	0x0204023C,
+	/* ALC256 Speaker output power - 4 ohm 2.2W (+12dB gain) + Combo Jack TRS setting */
+	0x02050038,
+	0x02047901,
+	0x02050045,
+	0x02045089,
+	/* H/W AGC setting-1 */
+	0x02050016,
+	0x02040C50,
+	0x02050012,
+	0x0204EBC2,
+	/* H/W AGC setting-2 */
+	0x02050013,
+	0x0204401D,
+	0x02050016,
+	0x02044E50,
+	/* Zero data  + EAPD to verb-control */
+	0x02050037,
+	0x0204FE15,
+	0x02050010,
+	0x02040020,
+	/* Zero data */
+	0x02050030,
+	0x02048000,
+	0x02050030,
+	0x02048000,
+	/* ALC256 default-3 */
+	0x05750003,
+	0x05740DA3,
+	0x02050046,
+	0x02040004,
+	/* ALC256 default-4 */
+	0x0205001B,
+	0x02040A4B,
+	0x02050008,
+	0x02046A6C,
+	/* JD1 */
+	0x02050009,
+	0x0204E003,
+	0x0205000A,
+	0x02047770,
+	/* Microphone + Array MIC  security Disable  +ADC clock Enable */
+	0x0205000D,
+	0x0204A020,
+	0x02050005,
+	0x02040700,
+	/* Speaker Enable */
+	0x0205000C,
+	0x020401EF,
+	0x0205000C,
+	0x020401EF,
+	/* EQ Bypass + EQ HPF cutoff 250Hz */
+	0x05350000,
+	0x0534201A,
+	0x0535001d,
+	0x05340800,
+	/* EQ-2 */
+	0x0535001e,
+	0x05340800,
+	0x05350003,
+	0x05341EF8,
+	/* EQ-3 */
+	0x05350004,
+	0x05340000,
+	0x05450000,
+	0x05442000,
+	/* EQ-4 */
+	0x0545001d,
+	0x05440800,
+	0x0545001e,
+	0x05440800,
+	/* EQ-5 */
+	0x05450003,
+	0x05441EF8,
+	0x05450004,
+	0x05440000,
+	/* EQ Update */
+	0x05350000,
+	0x0534E01A,
+	0x05350000,
+	0x0534E01A,
+
+	0x8086280b, /* Codec Vendor / Device ID: Intel */
+	0x80860101, /* Subsystem ID */
+	0x00000004, /* Number of 4 dword sets */
+
+	AZALIA_SUBVENDOR(2, 0x80860101),
+
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {
+};
+
+AZALIA_ARRAY_SIZES;
+
+#endif
diff --git a/src/mainboard/starlabs/labtop/variants/cml/romstage.c b/src/mainboard/starlabs/labtop/variants/cml/romstage.c
new file mode 100644
index 0000000000..389a91c25a
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/romstage.c
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <option.h>
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+#include <console/console.h>
+#include <gpio.h>
+#include <string.h>
+#include <types.h>
+
+#include "baseboard/memory.h"
+
+u8 get_memory_config_straps(void)
+{
+	/*
+	 * The hardware supports a number of different memory configurations
+	 * which are selected using four ID bits ID3 (GPP_H7), ID2 (GPP_H6),
+	 * ID1 (GPP_E23) and ID0 (GPP_E22).
+	 *
+	 * The mapping is defined in the schematics as follows ID3 is always
+	 * 0 and can be ignored):
+	 *
+	 * ID2ID1ID0Memory type
+	 * --------------------
+	 * 1  1  1 Samsung 4G single channel
+	 * 1  1  0 Samsung 8G dual channel
+	 * 1  0  1 Micron 4G single channel
+	 * 1  0  0 Micron 8G dual channel
+	 * 0  1  1 Hynix 4G single channel
+	 * 0  1  0 Hynix 8G dual channel
+	 * 0  0  1 Micron 16G dual channel
+	 * 0  0  0 Hynix 16G dual channel
+	 *
+	 * We return the value of these bits so that the index into the SPD
+	 * table can be .spd[] values can be configured correctly in the
+	 * memory configuration structure.
+	 */
+
+	gpio_t memid_gpios[] = {
+		GPP_E22,
+		GPP_E23,
+		GPP_H6
+	};
+	return (u8)gpio_base2_value(memid_gpios, ARRAY_SIZE(memid_gpios));
+}
+
+const struct cnl_mb_cfg *get_memory_cfg(struct cnl_mb_cfg *mem_cfg)
+{
+	u8 memid;
+
+	struct cnl_mb_cfg std_memcfg = {
+		/*
+		* The dqs_map arrays map the DDR4 pins to the SoC pins
+		* for both channels.
+		*
+		* the index = pin number on DDR4 part
+		* the value = pin number on SoC
+		*/
+		.dqs_map[DDR_CH0] = {0, 6, 1, 3, 5, 2, 7, 4},
+		.dqs_map[DDR_CH1] = {7, 5, 3, 6, 2, 4, 0, 1},
+
+		/*
+		* Mainboard uses 121, 81 and 100 rcomp resistors. See R6E1, R6E2
+		* and R6E3 on page 6 of the schematics.
+		*/
+		.rcomp_resistor = {121, 81, 100},
+
+		/*
+		* Mainboard Rcomp target values.
+		*/
+		.rcomp_targets = {100, 40, 20, 20, 26},
+
+		/*
+		* Mainboard is a non-interleaved design - see pages 5 & 6
+		* of the schematics.
+		*/
+		.dq_pins_interleaved = 0,
+
+		/*
+		* Mainboard is using DDR_VREF_CA for CH_A and DDR1_VREF_DQ for
+		* CH_B - see page 5 of the schematics.
+		*/
+		.vref_ca_config = 2,
+
+		/* Disable Early Command Training */
+		.ect = 0,
+	};
+
+	memcpy(mem_cfg, &std_memcfg, sizeof(std_memcfg));
+
+	memid = get_memory_config_straps();
+	printk(BIOS_DEBUG, "Memory config straps: 0x%.2x\n", memid);
+
+	/*
+	 * If we are using single channel ID = 3, 5 or 7 then we only
+	 * populate .spd[0].If we are dual channel then we also populate
+	 * .spd[2] as well.
+	 */
+	mem_cfg->spd[0].read_type = READ_SPD_CBFS;
+	mem_cfg->spd[0].spd_spec.spd_index = memid;
+	if (memid != 3 && memid != 5 && memid != 7) {
+		mem_cfg->spd[2].read_type = READ_SPD_CBFS;
+		mem_cfg->spd[2].spd_spec.spd_index = memid;
+	}
+
+	return mem_cfg;
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	struct cnl_mb_cfg board_memcfg;
+
+	const uint8_t vtd = get_uint_option("vtd", 1);
+	memupd->FspmTestConfig.VtdDisable = !vtd;
+	const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading);
+	memupd->FspmConfig.HyperThreading = ht;
+
+	cannonlake_memcfg_init(&memupd->FspmConfig, get_memory_cfg(&board_memcfg));
+}
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc b/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc
new file mode 100644
index 0000000000..e04a8dba30
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)
+
+romstage-y += romstage.c
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/board.fmd b/src/mainboard/starlabs/labtop/variants/kbl/board.fmd
new file mode 100644
index 0000000000..08bc519499
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/board.fmd
@@ -0,0 +1,13 @@
+#
+# Manually defined FMD in order to ensure that space is reserved for the EC
+# at the top of the BIOS region.
+#
+FLASH 8M {
+	BIOS@0x200000 0x600000 {
+		RW_MRC_CACHE@0x0 0x10000
+		SMMSTORE@0x10000 0x40000
+		CONSOLE@0x50000 0x20000
+		FMAP@0x70000 0x200
+		COREBOOT(CBFS)
+	}
+}
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/data.vbt b/src/mainboard/starlabs/labtop/variants/kbl/data.vbt
new file mode 100644
index 0000000000..b7146c52ec
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/data.vbt
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb
new file mode 100644
index 0000000000..d052352cea
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb
@@ -0,0 +1,203 @@
+chip soc/intel/skylake
+	# Disable DEEP
+	register "deep_s3_enable_ac" = "0"
+	register "deep_s3_enable_dc" = "0"
+	register "deep_s5_enable_ac" = "0"
+	register "deep_s5_enable_dc" = "0"
+	register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
+
+	# Enable "Intel Speed Shift Technology"
+	register "eist_enable" = "1"
+
+	# Disable DPTF
+	register "dptf_enable" = "0"
+
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+	}"
+
+	# Send an extra VR mailbox command for the PS4 exit issue
+	# register "SendVrMbxCmd" = "2"
+
+# Graphics (soc/intel/skylake/graphics.c)
+	register "panel_cfg" = "{
+		.up_delay_ms= 200,// T3
+		.down_delay_ms= 0,// T10
+		.cycle_delay_ms = 500,// T12
+		.backlight_on_delay_ms=50,// T7
+		.backlight_off_delay_ms = 0,// T9
+		.backlight_pwm_hz = 200,
+	}"
+
+	# IGD Displays
+	register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+
+# CPU (soc/intel/skylake/chip.c)
+	# Power limit
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 20,
+		.tdp_pl2_override = 30,
+	}"
+
+	# FSP configuration
+	register "SaGv" = "SaGv_Enabled"
+
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0]= PchSerialIoPci,
+		[PchSerialIoIndexI2C1]= PchSerialIoPci,
+		[PchSerialIoIndexI2C2]= PchSerialIoPci,
+		[PchSerialIoIndexI2C3]= PchSerialIoPci,
+		[PchSerialIoIndexI2C4]= PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5]= PchSerialIoPci,
+		[PchSerialIoIndexSpi0]= PchSerialIoPci,
+		[PchSerialIoIndexSpi1]= PchSerialIoPci,
+		[PchSerialIoIndexUart0] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUart1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
+	}"
+
+	# Power
+	register "PmConfigSlpS3MinAssert" = "3"		# 50ms
+	register "PmConfigSlpS4MinAssert" = "3"		# 1s
+	register "PmConfigSlpSusMinAssert" = "3"	# 500ms
+	register "PmConfigSlpAMinAssert" = "3"		# 2s
+
+	# Thermal
+	register "tcc_offset" = "5"
+
+# PM Util (soc/intel/skylake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "gpe0_dw0" = "GPP_B"
+	register "gpe0_dw1" = "GPP_C"
+	register "gpe0_dw2" = "GPP_E"
+
+	# Enable the correct decode ranges on the LPC bus.
+	register "lpc_ioe" = "LPC_IOE_EC_4E_4F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66"
+
+# Actual device tree.
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on  end			# Host Bridge
+		device pci 02.0 on  end			# Integrated Graphics Device
+		device pci 04.0 on  end			# SA Thermal Device
+		device pci 14.0 on			# USB xHCI
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C port 1
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"		# Type-A port 2
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
+			register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# uSD Card
+			register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"		# Type-A port 3
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"		# Camera
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Actual Bluetooth port
+
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
+		end
+		device pci 14.1 off end			# USB xDCI (OTG)
+		device pci 14.2 on  end			# Thermal Subsystem
+		device pci 15.0 on			# I2C #0
+			chip drivers/i2c/hid
+				register "generic.hid" = ""StarPoint""
+				register "generic.desc" = ""Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end
+		device pci 15.1 on  end	# I2C #1
+		device pci 15.2 off end	# I2C #2
+		device pci 15.3 off end	# I2C #3
+		device pci 16.0 on  end	# Management Engine Interface 1
+		device pci 16.1 off end	# Management Engine Interface 2
+		device pci 16.2 off end	# Management Engine IDE-R
+		device pci 16.3 off end	# Management Engine KT Redirection
+		device pci 16.4 off end	# Management Engine Interface 3
+		device pci 17.0 on	# SATA
+			register "SataSalpSupport" = "0"
+			register "SataMode" = "0"
+
+			# Port 1
+			register "SataPortsEnable[1]" = "1"
+			register "SataPortsDevSlp[1]" = "0"
+
+			# Port 2
+			register "SataPortsEnable[2]" = "1"
+			register "SataPortsDevSlp[2]" = "0"
+		end
+		device pci 19.0 on  end			# UART #2
+		device pci 19.1 off end			# I2C #4
+		device pci 19.2 off end			# I2C #5
+		device pci 1c.0 off end			# PCI Express Port 1
+		device pci 1c.1 off end			# PCI Express Port 2
+		device pci 1c.2 off end			# PCI Express Port 3
+		device pci 1c.3 off end			# PCI Express Port 4
+		device pci 1c.4 off end			# PCI Express Port 5
+		device pci 1c.5 on			# PCI Express Port 6 (WLAN)
+			register "PcieRpEnable[5]" = "1"
+			register "PcieRpClkReqSupport[5]" = "1"
+			register "PcieRpClkReqNumber[5]" = "4"
+			register "PcieRpClkSrcNumber[5]" = "4"
+			register "PcieRpLtrEnable[5]" = "1"
+			chip drivers/wifi/generic
+				device pci 00.0 on end
+			end
+		end
+		device pci 1c.6 off end			# PCI Express Port 7
+		device pci 1c.7 off end			# PCI Express Port 8
+		device pci 1d.0 on			# PCI Express Port 9(SSD x4)
+			device pci 00.0 on end
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqNumber[8]" = "0"
+			register "PcieRpClkSrcNumber[8]" = "0"
+			register "PcieRpLtrEnable[8]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
+		end
+		device pci 1d.1 off end			# PCI Express Port 10
+		device pci 1d.2 off end			# PCI Express Port 11
+		device pci 1d.3 off end			# PCI Express Port 12
+		device pci 1e.0 on  end			# UART #0
+		device pci 1e.1 off end			# UART #1
+		device pci 1e.2 off end			# GSPI #0
+		device pci 1e.3 off end			# GSPI #1
+		device pci 1e.4 off end			# eMMC
+		device pci 1e.5 off end			# SDIO
+		device pci 1e.6 off end			# SDCard
+		device pci 1f.0 on			# LPC Interface
+			# LPC configuration from lspci -s 1f.0 -xxx
+			# Address 0x84: Decode 0x680 - 0x68F
+			register "gen1_dec" = "0x000c0681"
+			# Address 0x88: Decode
+			register "gen2_dec" = "0x000c1641"
+			# Address 0x8C: Decode 0x200 - 0x2FF
+			register "gen3_dec" = "0x00000069"
+			# Address 0x90: Decode 0x80 - 0x8F (Port 80)
+			register "gen4_dec" = "0x0000006d"
+			register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+			chip ec/starlabs/it8987
+				# Port 4Eh/4Fh
+				device pnp 4e.0 on		# IO Interface
+				end
+			end
+		end
+		device pci 1f.1 off end			# P2SB
+		device pci 1f.2 on  end			# Power Management Controller
+		device pci 1f.3 on  end			# Intel HDA
+			subsystemid 0x10ec 0x111e
+		device pci 1f.4 on  end			# SMBus
+		device pci 1f.5 off end			# PCH SPI
+		device pci 1f.6 off end			# GbE
+	end
+end
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads b/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads
new file mode 100644
index 0000000000..8402b39a94
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads
@@ -0,0 +1,18 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1,   -- USB-C
+      HDMI1, -- USB-C
+      HDMI2, -- HDMI
+      eDP,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h
new file mode 100644
index 0000000000..803007d0f0
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _VARIANT_GPIO_H_
+#define _VARIANT_GPIO_H_
+
+#include "baseboard/variants.h"
+
+#ifndef __ACPI__
+
+/*
+ * All definitions are taken from a comparison of the output of "inteltool -a"
+ * using the stock BIOS and with coreboot.
+ */
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPD0, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD1, NONE, PWROK, NF1),
+	_PAD_CFG_STRUCT(GPD2, 0x04000300, 0x1000),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+	_PAD_CFG_STRUCT(GPD7, 0x04000101, 0x1000),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+	PAD_CFG_GPI(GPD9, DN_20K, PWROK),
+	PAD_CFG_NF(GPD10, DN_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD11, DN_20K, PWROK, NF1),
+	PAD_NC(GPP_A0, NONE),
+	PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+	PAD_NC(GPP_A7, NONE),
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+	PAD_NC(GPP_A10, DN_20K),
+	PAD_CFG_GPI(GPP_A11, DN_20K, DEEP),
+	PAD_NC(GPP_A12, NONE),
+	PAD_NC(GPP_A13, DN_20K),
+	PAD_NC(GPP_A14, DN_20K),
+	PAD_NC(GPP_A15, DN_20K),
+	PAD_NC(GPP_A16, DN_20K),
+	PAD_NC(GPP_A17, DN_20K),
+	PAD_NC(GPP_A18, DN_20K),
+	PAD_NC(GPP_A19, DN_20K),
+	PAD_NC(GPP_A20, DN_20K),
+	PAD_NC(GPP_A21, DN_20K),
+	PAD_NC(GPP_A22, DN_20K),
+	PAD_NC(GPP_A23, DN_20K),
+	PAD_NC(GPP_B0, DN_20K),
+	PAD_NC(GPP_B1, DN_20K),
+	PAD_NC(GPP_B2, DN_20K),
+	PAD_NC(GPP_B3, DN_20K),
+	PAD_CFG_TERM_GPO(GPP_B4, 1, UP_20K, DEEP),
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_B6, DN_20K, DEEP),
+	PAD_CFG_NF(GPP_B7, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_B8, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B10, DN_20K, DEEP, NF1),
+	PAD_NC(GPP_B11, DN_20K),
+	PAD_NC(GPP_B12, DN_20K),
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	PAD_NC(GPP_B14, DN_20K),
+	PAD_NC(GPP_B15, DN_20K),
+	PAD_NC(GPP_B16, DN_20K),
+	PAD_NC(GPP_B17, DN_20K),
+	PAD_NC(GPP_B18, DN_20K),
+	PAD_NC(GPP_B19, DN_20K),
+	PAD_NC(GPP_B20, DN_20K),
+	PAD_NC(GPP_B21, DN_20K),
+	PAD_NC(GPP_B22, DN_20K),
+	PAD_NC(GPP_B23, DN_20K),
+	PAD_CFG_NF(GPP_C0, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_C1, UP_20K, DEEP, NF1),
+	PAD_NC(GPP_C2, DN_20K),
+	PAD_NC(GPP_C3, DN_20K),
+	PAD_NC(GPP_C4, DN_20K),
+	PAD_NC(GPP_C5, DN_20K),
+	PAD_NC(GPP_C6, DN_20K),
+	PAD_NC(GPP_C7, DN_20K),
+	PAD_CFG_NF(GPP_C8, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_C9, UP_20K, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_C10, 0x44000301, 0x3000),
+	PAD_CFG_NF(GPP_C11, UP_20K, DEEP, NF1),
+	PAD_NC(GPP_C12, UP_20K),
+	PAD_NC(GPP_C13, UP_20K),
+	PAD_NC(GPP_C14, UP_20K),
+	PAD_NC(GPP_C15, UP_20K),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	PAD_NC(GPP_C22, NONE),
+	_PAD_CFG_STRUCT(GPP_C23, 0x80100100, 0x3000),
+	PAD_NC(GPP_D0, DN_20K),
+	PAD_NC(GPP_D1, DN_20K),
+	PAD_NC(GPP_D2, DN_20K),
+	PAD_NC(GPP_D3, DN_20K),
+	PAD_NC(GPP_D4, DN_20K),
+	PAD_NC(GPP_D5, DN_20K),
+	PAD_NC(GPP_D6, DN_20K),
+	PAD_NC(GPP_D7, DN_20K),
+	PAD_NC(GPP_D8, DN_20K),
+	PAD_NC(GPP_D9, DN_20K),
+	PAD_NC(GPP_D10, DN_20K),
+	PAD_NC(GPP_D11, DN_20K),
+	PAD_NC(GPP_D12, DN_20K),
+	PAD_NC(GPP_D13, DN_20K),
+	PAD_NC(GPP_D14, DN_20K),
+	PAD_NC(GPP_D15, DN_20K),
+	PAD_NC(GPP_D16, DN_20K),
+	PAD_NC(GPP_D17, DN_20K),
+	PAD_NC(GPP_D18, DN_20K),
+	PAD_NC(GPP_D19, DN_20K),
+	PAD_CFG_TERM_GPO(GPP_D20, 1, UP_20K, DEEP),
+	PAD_NC(GPP_D21, DN_20K),
+	PAD_NC(GPP_D22, DN_20K),
+	PAD_NC(GPP_D23, DN_20K),
+	PAD_NC(GPP_E0, DN_20K),
+	PAD_NC(GPP_E1, DN_20K),
+	_PAD_CFG_STRUCT(GPP_E2, 0x44000601, 0x0000),
+	PAD_NC(GPP_E3, DN_20K),
+	PAD_NC(GPP_E4, DN_20K),
+	PAD_NC(GPP_E5, DN_20K),
+	PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1),
+	PAD_NC(GPP_E7, DN_20K),
+	PAD_NC(GPP_E8, DN_20K),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+	PAD_NC(GPP_E12, DN_20K),
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0000),
+	_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000),
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
+	PAD_NC(GPP_E20, DN_20K),
+	PAD_NC(GPP_E21, DN_20K),
+	PAD_NC(GPP_E22, DN_20K),
+	PAD_NC(GPP_E23, DN_20K),
+	PAD_NC(GPP_F0, DN_20K),
+	PAD_NC(GPP_F1, DN_20K),
+	PAD_NC(GPP_F2, DN_20K),
+	PAD_NC(GPP_F3, DN_20K),
+	PAD_NC(GPP_F4, DN_20K),
+	PAD_NC(GPP_F5, DN_20K),
+	PAD_NC(GPP_F6, DN_20K),
+	PAD_NC(GPP_F7, DN_20K),
+	PAD_CFG_NF(GPP_F8, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F9, DN_20K, DEEP, NF1),
+	PAD_NC(GPP_F10, DN_20K),
+	PAD_NC(GPP_F11, DN_20K),
+	PAD_NC(GPP_F12, DN_20K),
+	PAD_NC(GPP_F13, DN_20K),
+	PAD_NC(GPP_F14, DN_20K),
+	PAD_NC(GPP_F15, DN_20K),
+	PAD_NC(GPP_F16, DN_20K),
+	PAD_NC(GPP_F17, DN_20K),
+	PAD_NC(GPP_F18, DN_20K),
+	PAD_NC(GPP_F19, DN_20K),
+	PAD_NC(GPP_F20, DN_20K),
+	PAD_NC(GPP_F21, DN_20K),
+	PAD_NC(GPP_F22, DN_20K),
+	PAD_NC(GPP_F23, DN_20K),
+	PAD_CFG_GPI(GPP_G0, DN_20K, DEEP),
+	PAD_CFG_GPI(GPP_G1, DN_20K, DEEP),
+	PAD_CFG_GPI(GPP_G2, DN_20K, DEEP),
+	PAD_CFG_GPI(GPP_G3, DN_20K, DEEP),
+	PAD_CFG_GPI(GPP_G4, DN_20K, DEEP),
+	PAD_CFG_GPI(GPP_G5, DN_20K, DEEP),
+	PAD_CFG_GPI(GPP_G6, DN_20K, DEEP),
+	PAD_CFG_GPI(GPP_G7, DN_20K, DEEP),
+
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+#endif
+
+#endif
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h
new file mode 100644
index 0000000000..2ad909624c
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _HDA_VERB_H_
+#define _HDA_VERB_H_
+
+#include <device/azalia_device.h>
+#include <device/azalia.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0269,	// Codec Vendor / Device ID: Realtek ALC269
+	0xffffffff,	// Subsystem ID
+	0x0000002b,	// Number of jacks (NID entries)
+	/* Rest Codec First */
+	AZALIA_RESET(0x1),
+	/* HDA Codec Subsystem ID Verb-table
+	HDA Codec Subsystem ID  : 0x10EC111E */
+	0x0017201E,
+	0x00172111,
+	0x001722EC,
+	0x00172310,
+	/* Pin Widget Verb-table */
+	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a61120),
+	AZALIA_PIN_CFG(0, 0x14, 0x90171110),
+	AZALIA_PIN_CFG(0, 0x15, 0x042B1010),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04AB1020),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x1A, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x1B, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x1D, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x1E, 0x411111F0),
+	/* Widget node 0x20 */
+	0x02050018,
+	0x02040184, /* Stock: 0x02043984 */
+	0x0205001C,
+	0x02040800,
+	/* Widget node 0x20 - 1 */
+	0x02050024,
+	0x02040000,
+	0x02050004,
+	0x02040080,
+	/* Widget node 0x20 - 2 */
+	0x02050008,
+	0x02040300,
+	0x0205000C,
+	0x02043F00,
+	/* Widget node 0x20 - 3 */
+	0x02050015,
+	0x02048002,
+	0x02050015,
+	0x02048002,
+	/* Widget node 0x0C */
+	0x00C37080,
+	0x00270610,
+	0x00D37080,
+	0x00370610,
+
+	0x8086280b,  /* Codec Vendor / Device ID: Intel */
+	0x80860101,  /* Subsystem ID */
+	0x00000004,  /* Number of 4 dword sets */
+
+	AZALIA_SUBVENDOR(2, 0x80860101),
+
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+
+};
+
+const u32 pc_beep_verbs[] = {
+};
+
+AZALIA_ARRAY_SIZES;
+
+#endif
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/romstage.c b/src/mainboard/starlabs/labtop/variants/kbl/romstage.c
new file mode 100644
index 0000000000..4f1b7e05d5
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/romstage.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <console/console.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include "spd/spd_util.c"
+#include "spd/spd.h"
+#include <ec/acpi/ec.h>
+#include <stdint.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
+	/* Use the correct entry in the SPD table defined in Makefile.inc */
+	u8 spd_index = 6;
+	printk(BIOS_INFO, "SPD index %d\n", spd_index);
+
+	mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
+	mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
+	mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+	mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+	mem_cfg->DqPinsInterleaved = 0;
+	mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
+	/* Memory leak is ok since we have memory mapped boot media */
+	// TODO evaluate google/eve way of loading
+	mem_cfg->MemorySpdPtr00 = spd_cbfs_map(spd_index);
+	if (!mem_cfg->MemorySpdPtr00)
+		die("spd.bin not found\n");
+	mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+
+	mupd->FspmTestConfig.DmiVc1 = 1;
+}