diff options
| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-09-24 09:03:06 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-09-24 09:03:06 +0000 |
| commit | 892b091e967cd2a54e23d22c8b37bfe12ebaaab5 (patch) | |
| tree | 6ea2802b10a9217c5c943b53bac44001f1e5389d /src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb | |
| parent | ac7a2d2f848928fba5054d37343754fc4b2d557d (diff) | |
Make all Kconfig enabled boards build (tested with kbuildall).
Also enable building individual boards with kbuildall for
debugging.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb')
| -rw-r--r-- | src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb b/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb new file mode 100644 index 0000000000..b51ebe6f81 --- /dev/null +++ b/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/ite/it8671f # Super I/O + device pnp 370.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 370.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 370.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 370.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 370.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 370.6 on # PS/2 mouse + irq 0x70 = 12 + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end |