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author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2020-10-24 01:36:00 +0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-27 16:35:24 +0000 |
commit | 5b511f98b5cd4ad03ae05fbcf5c1bdb665918cec (patch) | |
tree | 8ce9a5aa5b0840363a7bdd43e232891160bc1534 /src/mainboard/sifive | |
parent | fd3dde3e33c470b29ff953e82ca68f404d766bec (diff) |
mb/google/octopus/var/garg: Disable XHCI LFPS power management by sku
LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.
If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:171478764
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Change-Id: I213fed2b56f216747b2727b69f97d46d8c0c872e
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46701
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/sifive')
0 files changed, 0 insertions, 0 deletions