mb/siemens/mc_apl6: Add new mainboard based on mc_apl3

This patch adds a new mainboard variant called mc_apl6 which is based
on mc_apl3. So far only the names have been adjusted with no further
changes. Following commits will introduce the needed changes for this
mainboard variant.

Change-Id: Ic935f6cc1f037947b2c167696d40da8309e4d4f0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>

7 files changed, 663 insertions, 0 deletions

diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig
index 196ca28cdc..0b8cff3318 100644
--- a/src/mainboard/siemens/mc_apl1/Kconfig
+++ b/src/mainboard/siemens/mc_apl1/Kconfig
@@ -22,6 +22,7 @@ config VARIANT_DIR
 	default "mc_apl3" if BOARD_SIEMENS_MC_APL3
 	default "mc_apl4" if BOARD_SIEMENS_MC_APL4
 	default "mc_apl5" if BOARD_SIEMENS_MC_APL5
+	default "mc_apl6" if BOARD_SIEMENS_MC_APL6
 
 config DEVICETREE
 	string
@@ -34,6 +35,7 @@ config MAINBOARD_PART_NUMBER
 	default "MC APL3" if BOARD_SIEMENS_MC_APL3
 	default "MC APL4" if BOARD_SIEMENS_MC_APL4
 	default "MC APL5" if BOARD_SIEMENS_MC_APL5
+	default "MC APL6" if BOARD_SIEMENS_MC_APL6
 
 config UART_FOR_CONSOLE
 	default 2
diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name
index 70f314d985..225dd19d44 100644
--- a/src/mainboard/siemens/mc_apl1/Kconfig.name
+++ b/src/mainboard/siemens/mc_apl1/Kconfig.name
@@ -19,3 +19,7 @@ config BOARD_SIEMENS_MC_APL4
 config BOARD_SIEMENS_MC_APL5
 	bool "-> MC APL5"
 	select BOARD_SIEMENS_BASEBOARD_MC_APL1
+
+config BOARD_SIEMENS_MC_APL6
+	bool "-> MC APL6"
+	select BOARD_SIEMENS_BASEBOARD_MC_APL1
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig
new file mode 100644
index 0000000000..e0f2948a7d
--- /dev/null
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig
@@ -0,0 +1,12 @@
+
+if BOARD_SIEMENS_MC_APL6
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select DRIVER_INTEL_I210
+	select DRIVERS_I2C_RX6110SA
+	select DRIVER_SIEMENS_NC_FPGA
+	select NC_FPGA_NOTIFY_CB_READY
+	select APL_SKIP_SET_POWER_LIMITS
+
+endif # BOARD_SIEMENS_MC_APL6
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Makefile.inc
new file mode 100644
index 0000000000..a6b80e0832
--- /dev/null
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Makefile.inc
@@ -0,0 +1,4 @@
+romstage-y += gpio.c
+
+ramstage-y += gpio.c
+ramstage-y += mainboard.c
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
new file mode 100644
index 0000000000..e1e79b44ae
--- /dev/null
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
@@ -0,0 +1,107 @@
+chip soc/intel/apollolake
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	register "sci_irq" = "SCIS_IRQ10"
+
+	# Disable unused clkreq of PCIe root ports
+	register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
+
+	# EMMC TX DATA Delay 1
+	# Refer to EDS-Vol2-22.3.
+	# [14:8] steps of delay for HS400, each 125ps.
+	# [6:0] steps of delay for SDR104/HS200, each 125ps.
+	register "emmc_tx_data_cntl1" = "0x0C16"
+
+	# EMMC TX DATA Delay 2
+	# Refer to EDS-Vol2-22.3.
+	# [30:24] steps of delay for SDR50, each 125ps.
+	# [22:16] steps of delay for DDR50, each 125ps.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps.
+	# [6:0] steps of delay for SDR12, each 125ps.
+	register "emmc_tx_data_cntl2" = "0x28162828"
+
+	# EMMC RX CMD/DATA Delay 1
+	# Refer to EDS-Vol2-22.3.
+	# [30:24] steps of delay for SDR50, each 125ps.
+	# [22:16] steps of delay for DDR50, each 125ps.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps.
+	# [6:0] steps of delay for SDR12, each 125ps.
+	register "emmc_rx_cmd_data_cntl1" = "0x00181717"
+
+	# EMMC RX CMD/DATA Delay 2
+	# Refer to EDS-Vol2-22.3.
+	# [17:16] stands for Rx Clock before Output Buffer
+	# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
+	# [6:0] steps of delay for HS200, each 125ps.
+	register "emmc_rx_cmd_data_cntl2" = "0x10008"
+
+	# 0:HS400(Default), 1:HS200, 2:DDR50
+	register "emmc_host_max_speed" = "1"
+
+	device domain 0 on
+		device pci 00.0 on  end	# - Host Bridge
+		device pci 00.1 off end	# - DPTF
+		device pci 00.2 off end	# - NPK
+		device pci 02.0 on  end	# - Gen - Display
+		device pci 03.0 off end	# - Iunit
+		device pci 0d.0 on  end	# - P2SB
+		device pci 0d.1 off end	# - PMC
+		device pci 0d.2 on  end	# - SPI
+		device pci 0d.3 off end	# - Shared SRAM
+		device pci 0e.0 on  end	# - Audio
+		device pci 11.0 on  end	# - ISH
+		device pci 12.0 on  end	# - SATA
+		device pci 13.0 on  end	# - RP 2 - PCIe A 0
+		device pci 13.1 on  end	# - RP 3 - PCIe A 1
+		device pci 13.2 on  end	# - RP 4 - PCIe-A 2
+		device pci 13.3 on  end	# - RP 5 - PCIe-A 3
+		device pci 14.0 on  end	# - RP 0 - PCIe-B 0
+		device pci 14.1 on  end	# - RP 1 - PCIe-B 1
+		device pci 15.0 on  end	# - XHCI
+		device pci 15.1 off end	# - XDCI
+		device pci 16.0 on	# - I2C 0
+			# Enable external RTC chip
+			chip drivers/i2c/rx6110sa
+				register "pmon_sampling" = "PMON_SAMPL_256_MS"
+				register "bks_on" = "0"
+				register "bks_off" = "1"
+				register "iocut_en" = "1"
+				register "set_user_date" = "1"
+				register "user_year" = "04"
+				register "user_month" = "07"
+				register "user_day" = "01"
+				register "user_weekday" = "4"
+				device i2c 0x32 on end	# RTC RX6110 SA
+			end
+		end
+		device pci 16.1 off end	# - I2C 1
+		device pci 16.2 off end	# - I2C 2
+		device pci 16.3 off end	# - I2C 3
+		device pci 17.0 off end	# - I2C 4
+		device pci 17.1 off end	# - I2C 5
+		device pci 17.2 off end	# - I2C 6
+		device pci 17.3 off end	# - I2C 7
+		device pci 18.0 on  end	# - UART 0
+		device pci 18.1 on  end	# - UART 1
+		device pci 18.2 on  end	# - UART 2
+		device pci 18.3 on  end	# - UART 3
+		device pci 19.0 off end	# - SPI 0
+		device pci 19.1 off end	# - SPI 1
+		device pci 19.2 off end	# - SPI 2
+		device pci 1a.0 off end	# - PWM
+		device pci 1b.0 off end	# - SDCARD
+		device pci 1c.0 on  end	# - eMMC
+		device pci 1d.0 off end	# - UFS
+		device pci 1e.0 off end	# - SDIO
+		device pci 1f.0 on  end	# - LPC
+		device pci 1f.1 on  end	# - SMBUS
+	end
+end
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c
new file mode 100644
index 0000000000..7401c74a01
--- /dev/null
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c
@@ -0,0 +1,413 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ * Copyright (C) 2017-2018 Siemens AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <commonlib/helpers.h>
+#include <baseboard/variants.h>
+
+/*
+ * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
+ * table found in EDS vol 1, but some pins aren't grouped functionally in
+ * the table so those were moved for more logical grouping.
+ */
+static const struct pad_config gpio_table[] = {
+
+	/* Southwest Community */
+
+	/* PCIE_WAKE[0:3]_N */
+	PAD_CFG_NF(GPIO_205, NONE, DEEP, NF1),		/* PCIE_WAKE0_N */
+	PAD_CFG_NF(GPIO_206, NONE, DEEP, NF1),		/* PCIE_WAKE1_N */
+	PAD_CFG_NF(GPIO_207, NONE, DEEP, NF1),		/* PCIE_WAKE2_N */
+	PAD_CFG_NF(GPIO_208, NONE, DEEP, NF1),		/* PCIE_WAKE3_N */
+
+	/* EMMC interface. */
+	PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1),	/* EMMC_CLK */
+	PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1),	/* EMMC_D0 */
+	PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1),	/* EMMC_D1 */
+	PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1),	/* EMMC_D2 */
+	PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1),	/* EMMC_D3 */
+	PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1),	/* EMMC_D4 */
+	PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1),	/* EMMC_D5 */
+	PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1),	/* EMMC_D6 */
+	PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1),	/* EMMC_D7 */
+	PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1),	/* EMMC_CMD */
+	PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1),	/* EMMC_RCLK */
+
+	/* SDIO -- unused */
+	PAD_CFG_GPI(GPIO_166, DN_20K, DEEP),		/* SDIO_CLK */
+	PAD_CFG_GPI(GPIO_167, UP_20K, DEEP),		/* SDIO_D0 */
+	/* Configure SDIO to enable power gating. */
+	PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1),	/* SDIO_D1 */
+	PAD_CFG_GPI(GPIO_169, UP_20K, DEEP),		/* SDIO_D2 */
+	PAD_CFG_GPI(GPIO_170, UP_20K, DEEP),		/* SDIO_D3 */
+	PAD_CFG_GPI(GPIO_171, UP_20K, DEEP),		/* SDIO_CMD */
+
+	/* SDCARD */
+	/* Pull down clock by 20K. */
+	PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1),	/* SDCARD_CLK */
+	PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1),	/* SDCARD_D0 */
+	PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1),	/* SDCARD_D1 */
+	PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1),	/* SDCARD_D2 */
+	PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1),	/* SDCARD_D3 */
+	/* Card detect is active LOW with external pull up. */
+	PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1),	/* SDCARD_CD_N */
+	PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1),	/* SDCARD_CMD */
+	/* CLK feedback, internal signal, needs 20K pull down. */
+	PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1),	/* SDCARD_CLK_FB */
+	PAD_CFG_GPI(GPIO_186, UP_20K, DEEP),		/* SDCARD_LVL_WP */
+	/* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */
+	PAD_CFG_TERM_GPO(GPIO_183, 1, DN_20K, DEEP),	/* SDIO_PWR_DOWN_N */
+
+	/* SMBus */
+	PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP),		/* SMB_ALERT _N */
+	PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1),		/* SMB_CLK */
+	PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1),		/* SMB_DATA */
+
+	/* LPC */
+	PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1),	/* LPC_SERIRQ */
+	PAD_CFG_NF(LPC_CLKOUT0, DN_20K, DEEP, NF1),	/* LPC_CLKOUT0 */
+	PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP),		/* LPC_CLKOUT1 */
+	PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1),		/* LPC_AD0 */
+	PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1),		/* LPC_AD1 */
+	PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1),		/* LPC_AD2 */
+	PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1),		/* LPC_AD3 */
+	PAD_CFG_NF(LPC_CLKRUNB, NONE, DEEP, NF1),	/* LPC_CLKRUN_N */
+	PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1),	/* LPC_FRAME_N */
+
+	/* West Community */
+
+	/* I2C0 - I2C Level Shifter */
+	PAD_CFG_NF(GPIO_124, NONE, DEEP, NF1),		/* LPSS_I2C0_SDA */
+	PAD_CFG_NF(GPIO_125, NONE, DEEP, NF1),		/* LPSS_I2C0_SCL */
+
+	/* I2C[1:7] -- unused */
+	PAD_CFG_GPI(GPIO_126, UP_20K, DEEP),		/* LPSS_I2C1_SDA */
+	PAD_CFG_GPI(GPIO_127, UP_20K, DEEP),		/* LPSS_I2C1_SCL */
+	PAD_CFG_GPI(GPIO_128, UP_20K, DEEP),		/* LPSS_I2C2_SDA */
+	PAD_CFG_GPI(GPIO_129, UP_20K, DEEP),		/* LPSS_I2C2_SCL */
+	PAD_CFG_GPI(GPIO_130, UP_20K, DEEP),		/* LPSS_I2C3_SDA */
+	PAD_CFG_GPI(GPIO_131, UP_20K, DEEP),		/* LPSS_I2C3_SCL */
+	PAD_CFG_GPI(GPIO_132, UP_20K, DEEP),		/* LPSS_I2C4_SDA */
+	PAD_CFG_GPI(GPIO_133, UP_20K, DEEP),		/* LPSS_I2C4_SCL */
+	PAD_CFG_GPI(GPIO_134, UP_20K, DEEP),		/* LPSS_I2C5_SDA */
+	PAD_CFG_GPI(GPIO_135, UP_20K, DEEP),		/* LPSS_I2C5_SCL */
+	PAD_CFG_GPI(GPIO_136, UP_20K, DEEP),		/* LPSS_I2C6_SDA */
+	PAD_CFG_GPI(GPIO_137, UP_20K, DEEP),		/* LPSS_I2C6_SCL */
+	PAD_CFG_GPI(GPIO_138, UP_20K, DEEP),		/* LPSS_I2C7_SDA */
+	PAD_CFG_GPI(GPIO_139, UP_20K, DEEP),		/* LPSS_I2C7_SCL */
+
+	/* ISH_GPIO_[0:9] -- unused */
+	PAD_CFG_GPI(GPIO_146, DN_20K, DEEP),		/* ISH_GPIO_0 */
+	PAD_CFG_GPI(GPIO_147, DN_20K, DEEP),		/* ISH_GPIO_1 */
+	PAD_CFG_GPI(GPIO_148, DN_20K, DEEP),		/* ISH_GPIO_2 */
+	PAD_CFG_GPI(GPIO_149, DN_20K, DEEP),		/* ISH_GPIO_3 */
+	PAD_CFG_GPI(GPIO_150, DN_20K, DEEP),		/* ISH_GPIO_4 */
+	PAD_CFG_GPI(GPIO_151, DN_20K, DEEP),		/* ISH_GPIO_5 */
+	PAD_CFG_GPI(GPIO_152, DN_20K, DEEP),		/* ISH_GPIO_6 */
+	PAD_CFG_GPI(GPIO_153, DN_20K, DEEP),		/* ISH_GPIO_7 */
+	PAD_CFG_GPI(GPIO_154, DN_20K, DEEP),		/* ISH_GPIO_8 */
+	PAD_CFG_GPI(GPIO_155, DN_20K, DEEP),		/* ISH_GPIO_9 */
+
+	/* PCIE_CLKREQ[0:3]_N */
+	PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPIO_210, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPIO_211, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPIO_212, NONE, DEEP, NF1),
+
+	/* OSC_CLK_OUT_0 - RES_CLK_CPU_FPGA */
+	PAD_CFG_NF(OSC_CLK_OUT_0, DN_20K, DEEP, NF1),
+	/* OSC_CLK_OUT_[1:4] -- unused */
+	PAD_CFG_GPI(OSC_CLK_OUT_1, DN_20K, DEEP),
+	PAD_CFG_GPI(OSC_CLK_OUT_2, DN_20K, DEEP),
+	PAD_CFG_GPI(OSC_CLK_OUT_3, DN_20K, DEEP),
+	PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP),
+
+	/* PMU Signals */
+	PAD_CFG_GPI(PMU_AC_PRESENT, NONE, DEEP),	/* PMU_AC_PRESENT */
+	PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1),	/* PMU_BATLOW_N */
+	PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1),	/* PMU_PLTRST_N */
+	PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1),	/* PMU_PWRBTN_N */
+	PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1),	/* PMU_RSTBTN_N */
+	/* PMU_SLP_S0_N */
+	PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE),
+	PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1),	/* PMU_SLP_S3_N */
+	PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1),	/* PMU_SLP_S4_N */
+	PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1),	/* PMU_SUSCLK */
+	PAD_CFG_TERM_GPO(PMU_WAKE_B, 1, UP_20K, DEEP),	/* EN_PP3300_EMMC */
+	PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1),	/* SUS_STAT_N */
+	PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1),	/* SUSPWRDNACK */
+
+	/* Northwest Community */
+
+	/* DDI0 SDA and SCL -- unused */
+	PAD_CFG_GPI(GPIO_187, DN_20K, DEEP),		/* HV_DDI0_DDC_SDA */
+	PAD_CFG_GPI(GPIO_188, DN_20K, DEEP),		/* HV_DDI0_DDC_SCL */
+	/* DDI1 SDA and SCL - Display-Port */
+	PAD_CFG_NF(GPIO_189, NONE, DEEP, NF1),		/* HV_DDI1_DDC_SDA */
+	PAD_CFG_NF(GPIO_190, NONE, DEEP, NF1),		/* HV_DDI1_DDC_SCL */
+
+	/* MIPI I2C -- unused */
+	PAD_CFG_GPI(GPIO_191, DN_20K, DEEP),		/* MIPI_I2C_SDA */
+	PAD_CFG_GPI(GPIO_192, DN_20K, DEEP),		/* MIPI_I2C_SCL */
+
+	/* Panel 0 control -- unused */
+	PAD_CFG_TERM_GPO(GPIO_193, 0, DN_20K, DEEP),	/* PNL0_VDDEN */
+	PAD_CFG_TERM_GPO(GPIO_194, 0, DN_20K, DEEP),	/* PNL0_BKLTEN */
+	PAD_CFG_TERM_GPO(GPIO_195, 0, DN_20K, DEEP),	/* PNL0_BKLTCTL */
+
+	/* Panel 1 control -- unused */
+	PAD_CFG_GPI(GPIO_196, DN_20K, DEEP),		/* PNL1_VDDEN */
+	PAD_CFG_GPI(GPIO_197, DN_20K, DEEP),		/* PNL1_BKLTEN */
+	PAD_CFG_GPI(GPIO_198, DN_20K, DEEP),		/* PNL1_BKLTCTL */
+
+	/* DDI[0:1]_HPD -- unused */
+	PAD_CFG_GPI(GPIO_199, NONE, DEEP),		/* XHPD_DP */
+	PAD_CFG_GPI(GPIO_200, DN_20K, DEEP),		/* unused */
+
+	/* MDSI signals -- unused */
+	PAD_CFG_GPI(GPIO_201, DN_20K, DEEP),		/* MDSI_A_TE */
+	PAD_CFG_GPI(GPIO_202, DN_20K, DEEP),		/* MDSI_C_TE */
+
+	/* USB overcurrent pins. */
+	PAD_CFG_NF(GPIO_203, NONE, DEEP, NF1),		/* USB_OC0_N */
+	PAD_CFG_NF(GPIO_204, NONE, DEEP, NF1),		/* USB_OC1_N */
+
+	/* PMC SPI -- almost entirely unused. */
+	PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP),		/* CLP_NC */
+	PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2),	/* XHPD_EDP_APL */
+	PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP),
+	PAD_CFG_GPI(PMC_SPI_RXD, DN_20K, DEEP),
+	PAD_CFG_GPI(PMC_SPI_TXD, DN_20K, DEEP),
+	PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP),
+
+	/* PMIC Signals unused signals related to an old PMIC interface. */
+	PAD_CFG_NF(PMIC_PWRGOOD, UP_20K, DEEP, NF1),	/* PMIC_PWRGOOD */
+	PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP),	/* PMIC_RESET_B */
+	PAD_CFG_TERM_GPO(GPIO_213, 0, DN_20K, DEEP),	/* NFC_OUT_RESERVE */
+	PAD_CFG_TERM_GPO(GPIO_214, 0, DN_20K, DEEP),	/* NFC_EN */
+	PAD_CFG_GPI(GPIO_215, DN_20K, DEEP),		/* NFC_IN_RESERVE */
+	/* THERMTRIP_N */
+	PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1),
+	PAD_CFG_TERM_GPO(PMIC_STDBY, 0, DN_20K, DEEP),	/* unused */
+	PAD_CFG_NF(PROCHOT_B, NONE, DEEP, NF1),		/* PROCHOT_N */
+	PAD_CFG_NF(PMIC_I2C_SCL, NONE, DEEP, NF1),	/* PMIC_I2C_SCL */
+	PAD_CFG_NF(PMIC_I2C_SDA, NONE, DEEP, NF1),	/* PMIC_I2C_SDA */
+
+	/* I2S1 -- unused */
+	PAD_CFG_GPI(GPIO_74, DN_20K, DEEP),		/* I2S1_MCLK */
+	PAD_CFG_GPI(GPIO_75, DN_20K, DEEP),		/* I2S1_BCLK */
+	PAD_CFG_GPI(GPIO_76, DN_20K, DEEP),		/* I2S1_WS_SYNC */
+	PAD_CFG_GPI(GPIO_77, DN_20K, DEEP),		/* I2S1_SDI */
+	PAD_CFG_GPI(GPIO_78, DN_20K, DEEP),		/* I2S1_SDO */
+
+	/* DMIC or I2S4 -- unused */
+	PAD_CFG_GPI(GPIO_79, DN_20K, DEEP),		/* AVS_M_CLK_A1 */
+	PAD_CFG_GPI(GPIO_80, DN_20K, DEEP),		/* AVS_M_CLK_B1 */
+	PAD_CFG_GPI(GPIO_81, DN_20K, DEEP),		/* AVS_M_DATA_1 */
+	PAD_CFG_GPI(GPIO_82, DN_20K, DEEP),		/* AVS_M_CLK_AB2 */
+	PAD_CFG_GPI(GPIO_83, DN_20K, DEEP),		/* AVS_M_DATA_2 */
+
+	/* I2S2 -- unused */
+	PAD_CFG_GPI(GPIO_84, DN_20K, DEEP),		/* AVS_I2S2_MCLK */
+	PAD_CFG_GPI(GPIO_85, DN_20K, DEEP),		/* AVS_I2S2_BCLK */
+	PAD_CFG_GPI(GPIO_86, DN_20K, DEEP),		/* AVS_I2S2_WS_SYNC */
+	PAD_CFG_GPI(GPIO_87, DN_20K, DEEP),		/* AVS_I2S2_SDI */
+	PAD_CFG_GPI(GPIO_88, DN_20K, DEEP),		/* AVS_I2S2_SDO */
+
+	/* I2S3 -- unused */
+	PAD_CFG_GPI(GPIO_89, DN_20K, DEEP),		/* AVS_I2S3_BCLK */
+	PAD_CFG_GPI(GPIO_90, DN_20K, DEEP),		/* AVS_I2S3_WS_SYNC */
+	PAD_CFG_GPI(GPIO_91, DN_20K, DEEP),		/* AVS_I2S3_SDI */
+	PAD_CFG_GPI(GPIO_92, DN_20K, DEEP),		/* AVS_I2S3_SDO */
+
+	/* Fast SPI */
+	/* FST_SPI_CS0_B */
+	PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE),
+	/* FST_SPI_CS1_B -- unused */
+	PAD_CFG_GPI(GPIO_98, DN_20K, DEEP),
+	/* FST_SPI_MOSI_IO0 */
+	PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE),
+	/* FST_SPI_MISO_IO1 */
+	PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE),
+	/* FST_IO2 -- MEM_CONFIG0 */
+	PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1),
+	/* FST_IO3 -- MEM_CONFIG1 */
+	PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1),
+	/* FST_SPI_CLK */
+	PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE),
+	/* FST_SPI_CLK_FB */
+	PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE),
+
+	/* SIO_SPI_0 -- unused */
+	PAD_CFG_GPI(GPIO_104, DN_20K, DEEP),		/* GP_SSP_0_CLK */
+	PAD_CFG_GPI(GPIO_105, DN_20K, DEEP),		/* GP_SSP_0_FS0 */
+	PAD_CFG_GPI(GPIO_106, UP_20K, DEEP),		/* GP_SSP_0_FS1 */
+	PAD_CFG_GPI(GPIO_109, DN_20K, DEEP),		/* GP_SSP_0_RXD */
+	PAD_CFG_GPI(GPIO_110, DN_20K, DEEP),		/* GP_SSP_0_TXD */
+
+	/* SIO_SPI_1 -- unused */
+	PAD_CFG_GPI(GPIO_111, DN_20K, DEEP),		/* GP_SSP_1_CLK */
+	PAD_CFG_GPI(GPIO_112, DN_20K, DEEP),		/* GP_SSP_1_FS0 */
+	PAD_CFG_GPI(GPIO_113, DN_20K, DEEP),		/* GP_SSP_1_FS1 */
+	PAD_CFG_GPI(GPIO_116, DN_20K, DEEP),		/* GP_SSP_1_RXD */
+	PAD_CFG_GPI(GPIO_117, DN_20K, DEEP),		/* GP_SSP_1_TXD */
+
+	/* SIO_SPI_2 -- unused */
+	PAD_CFG_GPI(GPIO_118, DN_20K, DEEP),		/* GP_SSP_2_CLK */
+	PAD_CFG_GPI(GPIO_119, DN_20K, DEEP),		/* GP_SSP_2_FS0 */
+	PAD_CFG_GPI(GPIO_120, DN_20K, DEEP),		/* GP_SSP_2_FS1 */
+	PAD_CFG_GPI(GPIO_121, DN_20K, DEEP),		/* GP_SSP_2_FS2 */
+	PAD_CFG_GPI(GPIO_122, DN_20K, DEEP),		/* GP_SSP_2_RXD */
+	PAD_CFG_GPI(GPIO_123, NONE, DEEP),		/* GP_SSP_2_TXD */
+
+	/* North Community */
+
+	/* Debug tracing. */
+	PAD_CFG_GPI(GPIO_0, DN_20K, DEEP),	/* TRACE_0_CLK_VNN */
+	PAD_CFG_GPI(GPIO_1, DN_20K, DEEP),	/* TRACE_0_DATA0_VNN */
+	PAD_CFG_GPI(GPIO_2, DN_20K, DEEP),	/* TRACE_0_DATA1_VNN */
+	PAD_CFG_GPI(GPIO_3, DN_20K, DEEP),	/* TRACE_0_DATA2_VNN */
+	PAD_CFG_GPI(GPIO_4, DN_20K, DEEP),	/* TRACE_0_DATA3_VNN */
+	PAD_CFG_GPI(GPIO_5, DN_20K, DEEP),	/* TRACE_0_DATA4_VNN */
+	PAD_CFG_GPI(GPIO_6, DN_20K, DEEP),	/* TRACE_0_DATA5_VNN */
+	PAD_CFG_GPI(GPIO_7, DN_20K, DEEP),	/* TRACE_0_DATA6_VNN */
+	PAD_CFG_GPI(GPIO_8, DN_20K, DEEP),	/* TRACE_0_DATA7_VNN */
+
+	PAD_CFG_GPI(GPIO_9, DN_20K, DEEP),	/* TRACE_1_CLK_VNN */
+	PAD_CFG_GPI(GPIO_10, DN_20K, DEEP),	/* TRACE_1_DATA0_VNN */
+	PAD_CFG_GPI(GPIO_11, DN_20K, DEEP),	/* TRACE_1_DATA1_VNN */
+	PAD_CFG_GPI(GPIO_12, DN_20K, DEEP),	/* TRACE_1_DATA2_VNN */
+	PAD_CFG_GPI(GPIO_13, DN_20K, DEEP),	/* TRACE_1_DATA3_VNN */
+	PAD_CFG_GPI(GPIO_14, DN_20K, DEEP),	/* TRACE_1_DATA4_VNN */
+	PAD_CFG_GPI(GPIO_15, DN_20K, DEEP),	/* TRACE_1_DATA5_VNN */
+	PAD_CFG_GPI(GPIO_16, DN_20K, DEEP),	/* TRACE_1_DATA6_VNN */
+	PAD_CFG_GPI(GPIO_17, DN_20K, DEEP),	/* TRACE_1_DATA7_VNN */
+
+	PAD_CFG_GPI(GPIO_18, DN_20K, DEEP),	/* TRACE_2_CLK_VNN */
+	PAD_CFG_GPI(GPIO_19, DN_20K, DEEP),	/* TRACE_2_DATA0_VNN */
+	PAD_CFG_GPI(GPIO_20, DN_20K, DEEP),	/* TRACE_2_DATA1_VNN */
+	PAD_CFG_GPI(GPIO_21, DN_20K, DEEP),	/* TRACE_2_DATA2_VNN */
+	PAD_CFG_GPI(GPIO_22, DN_20K, DEEP),	/* TRACE_2_DATA3_VNN */
+	PAD_CFG_GPI(GPIO_23, DN_20K, DEEP),	/* TRACE_2_DATA4_VNN */
+	PAD_CFG_GPI(GPIO_24, DN_20K, DEEP),	/* TRACE_2_DATA5_VNN */
+	PAD_CFG_GPI(GPIO_25, DN_20K, DEEP),	/* TRACE_2_DATA6_VNN */
+	PAD_CFG_GPI(GPIO_26, DN_20K, DEEP),	/* TRACE_2_DATA7_VNN */
+
+	PAD_CFG_GPI(GPIO_27, DN_20K, DEEP),	/* TRIGOUT_0 */
+	PAD_CFG_GPI(GPIO_28, DN_20K, DEEP),	/* TRIGOUT_1 */
+	PAD_CFG_GPI(GPIO_29, DN_20K, DEEP),	/* TRIGIN_0 */
+
+	PAD_CFG_GPI(GPIO_30, DN_20K, DEEP),		/* ISH_GPIO_12 */
+	PAD_CFG_TERM_GPO(GPIO_31, 1, UP_20K, DEEP),	/* ISH_GPIO_13 */
+	PAD_CFG_GPI(GPIO_32, UP_20K, DEEP),		/* ISH_GPIO_14 */
+	PAD_CFG_GPI(GPIO_33, DN_20K, DEEP),		/* ISH_GPIO_15 */
+
+	/* PWM[0:3] -- unused */
+	PAD_CFG_GPI(GPIO_34, DN_20K, DEEP),
+	PAD_CFG_GPI(GPIO_35, DN_20K, DEEP),
+	PAD_CFG_GPI(GPIO_36, DN_20K, DEEP),
+	PAD_CFG_GPI(GPIO_37, DN_20K, DEEP),
+
+	/* LPSS_UART[0:2] */
+	PAD_CFG_GPI(GPIO_38, UP_20K, DEEP),	/* LPSS_UART0_RXD - unused */
+	PAD_CFG_GPI(GPIO_39, DN_20K, DEEP),	/* LPSS_UART0_TXD - unused */
+	PAD_CFG_GPI(GPIO_40, DN_20K, DEEP),	/* LPSS_UART0_RTS - unused */
+	PAD_CFG_GPI(GPIO_41, UP_20K, DEEP),	/* LPSS_UART0_CTS - unused */
+	PAD_CFG_NF(GPIO_42, UP_20K, DEEP, NF1), /* LPSS_UART1_RXD */
+	/* LPSS_UART1_TXD */
+	PAD_CFG_NF_IOSSTATE(GPIO_43, NATIVE, DEEP, NF1, Tx1RxDCRx0),
+	PAD_CFG_GPI(GPIO_44, UP_20K, DEEP),	/* LPSS_UART1_RTS - unused */
+	PAD_CFG_GPI(GPIO_45, UP_20K, DEEP),	/* LPSS_UART1_CTS - unused */
+	PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1),	/* LPSS_UART2_RXD */
+	/* LPSS_UART2_TXD */
+	PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0),
+	PAD_CFG_GPI(GPIO_48, DN_20K, DEEP),	/* LPSS_UART2_RTS - unused */
+	PAD_CFG_GPI(GPIO_49, UP_20K, DEEP),	/* LPSS_UART2_CTS - unused */
+
+	/* Camera interface -- completely unused. */
+	PAD_CFG_GPI(GPIO_62, DN_20K, DEEP),	/* GP_CAMERASB00 */
+	PAD_CFG_GPI(GPIO_63, DN_20K, DEEP),	/* GP_CAMERASB01 */
+	PAD_CFG_GPI(GPIO_64, DN_20K, DEEP),	/* GP_CAMERASB02 */
+	PAD_CFG_GPI(GPIO_65, DN_20K, DEEP),	/* GP_CAMERASB03 */
+	PAD_CFG_GPI(GPIO_66, DN_20K, DEEP),	/* GP_CAMERASB04 */
+	PAD_CFG_GPI(GPIO_67, DN_20K, DEEP),	/* GP_CAMERASB05 */
+	PAD_CFG_GPI(GPIO_68, DN_20K, DEEP),	/* GP_CAMERASB06 */
+	PAD_CFG_GPI(GPIO_69, DN_20K, DEEP),	/* GP_CAMERASB07 */
+	PAD_CFG_GPI(GPIO_70, UP_20K, DEEP),	/* GP_CAMERASB08 */
+	PAD_CFG_GPI(GPIO_71, UP_20K, DEEP),	/* GP_CAMERASB09 */
+	PAD_CFG_GPI(GPIO_72, UP_20K, DEEP),	/* GP_CAMERASB10 */
+	PAD_CFG_GPI(GPIO_73, UP_20K, DEEP),	/* GP_CAMERASB11 */
+
+	/* CNV bridge described into IAFW Vol2. */
+	/* GPIO_[216:219] described into EDS Vol1. */
+	PAD_CFG_TERM_GPO(CNV_BRI_DT, 0, DN_20K, DEEP),	/* Reserve of FPGA */
+	PAD_CFG_TERM_GPO(CNV_BRI_RSP, 0, DN_20K, DEEP),	/* Reserve of FPGA */
+	PAD_CFG_TERM_GPO(CNV_RGI_DT, 0, DN_20K, DEEP),	/* Reserve of FPGA */
+	PAD_CFG_NF(CNV_RGI_RSP, UP_20K, DEEP, NF1),	/* eMMC */
+
+	/* Serial VID */
+	PAD_CFG_NF(SVID0_ALERT_B, NONE, DEEP, NF1),	/* SVID0_ALERT_B */
+	PAD_CFG_NF(SVID0_DATA, UP_20K, DEEP, NF1),	/* SVID0_DATA */
+	PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1),	/* SVID0_CLK */
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+/* GPIOs needed prior to ramstage. */
+static const struct pad_config early_gpio_table[] = {
+
+	/* Debug tracing. */
+	PAD_CFG_GPI(GPIO_0, DN_20K, DEEP),	/* TRACE_0_CLK_VNN */
+	PAD_CFG_GPI(GPIO_1, DN_20K, DEEP),	/* TRACE_0_DATA0_VNN */
+	PAD_CFG_GPI(GPIO_2, DN_20K, DEEP),	/* TRACE_0_DATA1_VNN */
+	PAD_CFG_GPI(GPIO_3, DN_20K, DEEP),	/* TRACE_0_DATA2_VNN */
+	PAD_CFG_GPI(GPIO_4, DN_20K, DEEP),	/* TRACE_0_DATA3_VNN */
+	PAD_CFG_GPI(GPIO_5, DN_20K, DEEP),	/* TRACE_0_DATA4_VNN */
+	PAD_CFG_GPI(GPIO_6, DN_20K, DEEP),	/* TRACE_0_DATA5_VNN */
+	PAD_CFG_GPI(GPIO_7, DN_20K, DEEP),	/* TRACE_0_DATA6_VNN */
+	PAD_CFG_GPI(GPIO_8, DN_20K, DEEP),	/* TRACE_0_DATA7_VNN */
+
+	PAD_CFG_GPO(GPIO_13, 0, DEEP),		/* PERST# */
+	PAD_CFG_GPO(GPIO_15, 0, DEEP),		/* PERST# */
+	PAD_CFG_GPO(GPIO_17, 1, DEEP),		/* PFET */
+	PAD_CFG_GPO(GPIO_19, 1, DEEP),		/* PFET */
+	PAD_CFG_GPO(GPIO_152, 0, DEEP),		/* PERST# */
+
+	/* SMBus */
+	PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1),	/* SMB_CLK */
+	PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1),	/* SMB_DATA */
+
+	/* LPC */
+	PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1),	/* LPC_SERIRQ */
+	PAD_CFG_NF(LPC_CLKOUT0, DN_20K, DEEP, NF1),	/* LPC_CLKOUT0 */
+	/* LPC_CLKOUT1 - unused */
+	PAD_CFG_GPI(LPC_CLKOUT1, DN_20K, DEEP),
+	PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1),		/* LPC_AD0 */
+	PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1),		/* LPC_AD1 */
+	PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1),		/* LPC_AD2 */
+	PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1),		/* LPC_AD3 */
+	PAD_CFG_NF(LPC_CLKRUNB, NONE, DEEP, NF1),	/* LPC_CLKRUN_N */
+	PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1),	/* LPC_FRAME_N */
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
new file mode 100644
index 0000000000..6a883c6a26
--- /dev/null
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Siemens AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <bootstate.h>
+#include <cf9_reset.h>
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <gpio.h>
+#include <hwilib.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+#include <timer.h>
+#include <timestamp.h>
+#include <baseboard/variants.h>
+#include <types.h>
+
+#define TX_DWORD3	0xa8c
+
+void variant_mainboard_final(void)
+{
+	struct device *dev = NULL;
+	uint16_t cmd = 0;
+
+	/* PIR6 register mapping for PCIe root ports
+	 * INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC#
+	 */
+	pcr_write16(PID_ITSS, 0x314c, 0x2103);
+
+	/* Enable CLKRUN_EN for power gating LPC */
+	lpc_enable_pci_clk_cntl();
+
+	/*
+	 * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2
+	 * offset 0x341D bit3 and bit0.
+	 * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2
+	 * offset 0x341C bit [3:0].
+	 */
+	pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
+
+	/* Set Master Enable for on-board PCI device. */
+	dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0);
+	if (dev) {
+		cmd = pci_read_config16(dev, PCI_COMMAND);
+		cmd |= PCI_COMMAND_MASTER;
+		pci_write_config16(dev, PCI_COMMAND, cmd);
+
+		/* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream
+		 * XIO2001 PCIe to PCI Bridge.
+		 */
+		struct device *parent = dev->bus->dev;
+		if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001)
+			pci_write_config8(parent, 0xd8, 0x1d);
+	}
+
+	/* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI
+	 * Bridge on this mainboard.
+	 */
+	dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0);
+	if (dev) {
+		struct device *parent = dev->bus->dev;
+		if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001)
+			pci_write_config8(parent, 0xd8, 0x3c);
+	}
+
+	/* Set Full Reset Bit in Reset Control Register (I/O port CF9h).
+	 * When Bit 3 is set to 1 and then the reset button is pressed the PCH
+	 * will drive SLP_S3 active (low). SLP_S3 is then used on the mainboard
+	 * to generate the right reset timing.
+	 */
+	outb(FULL_RST, RST_CNT);
+}
+
+static void wait_for_legacy_dev(void *unused)
+{
+	uint32_t legacy_delay, us_since_boot;
+	struct stopwatch sw;
+
+	/* Open main hwinfo block. */
+	if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)
+		return;
+
+	/* Get legacy delay parameter from hwinfo. */
+	if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay,
+			      sizeof(legacy_delay)) != sizeof(legacy_delay))
+		return;
+
+	us_since_boot = get_us_since_boot();
+	/* No need to wait if the time since boot is already long enough.*/
+	if (us_since_boot > legacy_delay)
+		return;
+	stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000);
+	printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...",
+			legacy_delay - us_since_boot, legacy_delay);
+	stopwatch_wait_until_expired(&sw);
+	printk(BIOS_NOTICE, "done!\n");
+}
+
+static void finalize_boot(void *unused)
+{
+	/* Set coreboot ready LED. */
+	gpio_output(CNV_RGI_DT, 1);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL);
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);