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authorMario Scheithauer <mario.scheithauer@siemens.com>2023-03-17 09:56:55 +0100
committerLean Sheng Tan <sheng.tan@9elements.com>2023-03-21 11:17:14 +0000
commit1af4b289f06b6f8b9eb14b4754bedd3fbce944bf (patch)
tree92d0bdd09e425261d994fc81ad13c596d9f5c9cb /src/mainboard/siemens
parent4f37cf0735f94ede56f060cacf1d2f0d1a1289e3 (diff)
mb/siemens/mc_ehl4: Enable PCIe devices
Correct the remaining PCI devices, differing from the ehl1 mainboard. Change-Id: Ie09188b72a62c4d5cba2fcda6f60f3bc0098633e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Diffstat (limited to 'src/mainboard/siemens')
-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
index f9dd8302ad..1bf99fd837 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
@@ -44,14 +44,14 @@ chip soc/intel/elkhartlake
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
- register "PcieRpEnable[6]" = "1"
+ register "PcieRpEnable[4]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
- register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
- register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"
- register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
+ register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE"
+ register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
+ register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE"
register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
@@ -65,14 +65,14 @@ chip soc/intel/elkhartlake
register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[3]" = "L1_SS_DISABLED"
- register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"
+ register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
# Disable LTR for all PCIe root ports
register "PcieRpLtrDisable[0]" = "true"
register "PcieRpLtrDisable[1]" = "true"
register "PcieRpLtrDisable[2]" = "true"
register "PcieRpLtrDisable[3]" = "true"
- register "PcieRpLtrDisable[6]" = "true"
+ register "PcieRpLtrDisable[4]" = "true"
# Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "0"
@@ -159,7 +159,7 @@ chip soc/intel/elkhartlake
device pci 1c.1 on end # RP2 (pcie0 single VC)
device pci 1c.2 on end # RP3 (pcie0 single VC)
device pci 1c.3 on end # RP4 (pcie0 single VC)
- device pci 1c.6 on end # RP7 (pcie3 multi VC)
+ device pci 1c.4 on end # RP5 (pcie1 multi VC)
device pci 1e.0 on end # UART0
device pci 1e.1 on end # UART1