diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2022-05-16 16:21:51 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-17 21:08:47 +0000 |
| commit | da541327d2ecfc9043205a7bd81c0ed71c4313fa (patch) | |
| tree | f8f915a71c748ab9e871a122340ad6ddf4109ae5 /src/mainboard/siemens/mc_ehl | |
| parent | 46af7f7442f53939130ed2eda2c00bb72cfa7746 (diff) | |
soc/intel/elkhartlake: Enable SMBus depending on dev state
Program the `SmbusEnable` FSP UPD according to the SMBus PCI device's
state in the devicetree. This avoids having to manually make sure the
SMBus PCI device and the `SmbusEnable` setting are in sync.
Change-Id: I275a981f914a55dc57a75e7d436912ff0255a293
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64402
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens/mc_ehl')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index d7c3e22f3b..9bb8d8f328 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -14,7 +14,6 @@ chip soc/intel/elkhartlake # FSP configuration register "SaGv" = "SaGv_Disabled" - register "SmbusEnable" = "1" # Enable IBECC for the complete memory register "ibecc" = "{ diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index f74b504e0d..72e4f60cd3 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -14,7 +14,6 @@ chip soc/intel/elkhartlake # FSP configuration register "SaGv" = "SaGv_Disabled" - register "SmbusEnable" = "1" # Enable IBECC for the complete memory register "ibecc" = "{ |