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| author | Angel Pons <th3fanbus@gmail.com> | 2021-10-12 21:01:13 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-10-14 11:17:52 +0000 |
| commit | d4ba2b14caf61a8a9716a6525b8e4313f6121e7b (patch) | |
| tree | c243b7cee76f9e9a6bfcf75ec27d50cd7dcdba55 /src/mainboard/siemens/mc_ehl | |
| parent | 5412a81485b27a04c004acdb623d017ffa9bb587 (diff) | |
sb/intel/lynxpoint: Enable PCIe Clock PM and ASPM L1
Enable PCIe Clock power management and ASPM L1 substate by default. This
matches what Broadwell does.
Change-Id: Ic2bbcbc23d6bab0900d3e90ad8e2fbfa4aea3c16
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/siemens/mc_ehl')
0 files changed, 0 insertions, 0 deletions