diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2019-01-29 08:54:52 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-30 11:01:01 +0000 |
| commit | 9ca43191ab454c777102f9634b5d40478cd4dc58 (patch) | |
| tree | 5f6cd88a169851db8bca8dce6c3b6f0daa6b4b21 /src/mainboard/siemens/mc_apl1 | |
| parent | ddf84986d540e275cee906933637480f526530a5 (diff) | |
siemens/mc_apl2: Change SERIRQ mode
Because of Intel's faulty LPC clock, the SERIRQ mode must be corrected.
By removing this entry from devicetree, the default value (quiet mode)
is used. The problem is described in Intel document 334820-007 under
point APL47.
Change-Id: I7a45e0e5fcde17a20abd19a33282b8a9215b1480
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31138
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index e54444ac65..c362e6c0a9 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -5,7 +5,6 @@ chip soc/intel/apollolake end register "sci_irq" = "SCIS_IRQ10" - register "serirq_mode" = "SERIRQ_CONTINUOUS" # Disable all clkreq of PCIe root ports as SMARC interface do not # have this pins. |