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authorMario Scheithauer <mario.scheithauer@siemens.com>2018-08-23 15:33:53 +0200
committerWerner Zeh <werner.zeh@siemens.com>2018-08-31 04:11:43 +0000
commite27c096b7f20e5f5424f1e912d7a88d820285e71 (patch)
tree9eaff5bee3ab14985a9d878480f2950d9522e5ef /src/mainboard/siemens/mc_apl1
parentaef592d9b66aa18d83b0a211ead26013ff1f7d98 (diff)
siemens/mc_apl1: Correct the Tx signal from SATA interface
Because of an incorrect transmit voltage swing, the signal must be adjusted. The factor of slices for full swing level can be corrected via the High Speed I/O Transmit Control Register 3. Change-Id: I116802cd2a944658fc3022e948eba43cebe52bb4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1')
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
index 099b67b01d..6d22fd9826 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
@@ -27,6 +27,8 @@
#include <baseboard/variants.h>
#include <variant/ptn3460.h>
+#define TX_DWORD3 0xa8c
+
void variant_mainboard_final(void)
{
int status;
@@ -63,6 +65,14 @@ void variant_mainboard_final(void)
* offset 0x341C bit [3:0].
*/
pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
+
+ /*
+ * Correct the SATA transmit signal via the High Speed I/O Transmit
+ * Control Register 3.
+ * Bit [23:16] set the output voltage swing for TX line.
+ * The value 0x4a sets the swing level to 0.58 V.
+ */
+ pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16));
}
static void wait_for_legacy_dev(void *unused)