siemens/mc_apl1: Make the DDR memory swizzle data configurable

In preparation for a future MC Apollo Lake board which will be equipped
with LPDDR4 modules, it is necessary to make the swizzle data
configurable. Starting from the mc_apl1 baseboard, which is equipped
with DDR3L memory and therefore does not need swizzle data, the
structures are initialized with zero.

Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

3 files changed, 73 insertions, 0 deletions

diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc
index e3e87ce71f..07ebf9b049 100644
--- a/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc
+++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc
@@ -1,3 +1,4 @@
 romstage-y += gpio.c
+romstage-y += memory.c
 
 ramstage-y += gpio.c
diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h b/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h
index 09153c6c33..6828ed81e3 100644
--- a/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h
@@ -26,6 +26,9 @@
 const struct pad_config *variant_gpio_table(size_t *num);
 const struct pad_config *variant_early_gpio_table(size_t *num);
 
+/* This function provides the swizzle data for the DRAM initialization. */
+const struct lpddr4_swizzle_cfg *variant_lpddr4_swizzle_config(void);
+
 /* The following function performs board specific things. */
 void variant_mainboard_final(void);
 
diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c
new file mode 100644
index 0000000000..13b7ab8cd3
--- /dev/null
+++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ * Copyright (C) 2018 Siemens AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <compiler.h>
+#include <soc/meminit.h>
+
+const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = {
+	/* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
+	.phys[LP4_PHYS_CH0A] = {
+		/* DQA[0:7] pins of LPDDR4 module. */
+		.dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 },
+		/* DQA[8:15] pins of LPDDR4 module. */
+		.dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 },
+		/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+		.dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 },
+		/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+		.dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 },
+	},
+	.phys[LP4_PHYS_CH0B] = {
+		/* DQA[0:7] pins of LPDDR4 module. */
+		.dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 },
+		/* DQA[8:15] pins of LPDDR4 module. */
+		.dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 },
+		/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+		.dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 },
+		/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+		.dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 },
+	},
+	.phys[LP4_PHYS_CH1A] = {
+		/* DQA[0:7] pins of LPDDR4 module. */
+		.dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 },
+		/* DQA[8:15] pins of LPDDR4 module. */
+		.dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 },
+		/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+		.dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 },
+		/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+		.dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 },
+	},
+	.phys[LP4_PHYS_CH1B] = {
+		/* DQA[0:7] pins of LPDDR4 module. */
+		.dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 },
+		/* DQA[8:15] pins of LPDDR4 module. */
+		.dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 },
+		/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+		.dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 },
+		/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+		.dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 },
+	},
+};
+
+const struct lpddr4_swizzle_cfg * __weak variant_lpddr4_swizzle_config(void)
+{
+	return &baseboard_lpddr4_swizzle;
+}