diff options
author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2019-07-10 13:15:54 +0200 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2019-07-11 15:14:06 +0000 |
commit | 1f21a96c842c285308fd0b433a578ce101483aa1 (patch) | |
tree | 670d53d31be99ee8ce68536a80b265f23bfc7b7c /src/mainboard/siemens/mc_apl1/variants/mc_apl4 | |
parent | badbcde5425b587fe23f8bd6ce02c740913fdd1d (diff) |
mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed mode
We need to reduce the eMMC bus speed for these Apollo Lake mainboards
because of a limitation on Intel side for industry use cases.
Change-Id: Ide6a1a302001c0752d149bfdab175a27c8f8cc35
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1/variants/mc_apl4')
-rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 50207e0e54..fc9885ce7f 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -45,7 +45,7 @@ chip soc/intel/apollolake register "emmc_rx_cmd_data_cntl2" = "0x10008" # 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "2" + register "emmc_host_max_speed" = "1" device domain 0 on device pci 00.0 on end # - Host Bridge |