diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2021-01-14 14:54:38 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-20 12:26:42 +0000 |
| commit | 92e4ed170232dd6e460be996772f07a26e620677 (patch) | |
| tree | d3ae07243c2130e250dfa4594e6b08f5c5ee533e /src/mainboard/siemens/mc_apl1/variants/mc_apl3 | |
| parent | 1bc061ee90bf87b89c93913b9116ad5a842e8b6a (diff) | |
mb/siemens/{mc_apl1,...,mc_apl6}: Configure FSP-S UPDs
Until now some FSP-S parameters were configured for Siemens APL
mainboards via the Binary Configuration Tool (BCT). For simplification,
the original APL FSP binary should now be used. For this purpose, the
corresponding FSP-S parameters are set via devicetree, respectively via
mainboard_silicon_init_params accordingly.
The following parameters are affected:
- Disable CPU power states (C-states)
- Set lowest Max Pkg Cstate - PkgC0C1
- Disable PCIe Hot Plug for all enabled RPs
- Disable PCIe Transmitter Half Swing for all RPs
- Disable PCIe Active State Power Management (ASPM) for all RPs
- Disable PCIe L1 Substates for all RPs
TEST:
- Compare old with new coreboot log on mc_apl5, found no differences
- Boot Linux v4.4 and check output of 'lspci'
Change-Id: I5af627defd6426140cc9a74bb18db400a8971d72
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1/variants/mc_apl3')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb | 38 |
1 files changed, 24 insertions, 14 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index bc5a9cf6a7..66ff911a95 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -6,14 +6,6 @@ chip soc/intel/apollolake register "sci_irq" = "SCIS_IRQ10" - # Disable unused clkreq of PCIe root ports - register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-22.3. # [14:8] steps of delay for HS400, each 125ps. @@ -60,12 +52,30 @@ chip soc/intel/apollolake device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA - device pci 13.0 on end # - RP 2 - PCIe A 0 - device pci 13.1 on end # - RP 3 - PCIe A 1 - device pci 13.2 on end # - RP 4 - PCIe-A 2 - device pci 13.3 on end # - RP 5 - PCIe-A 3 - device pci 14.0 on end # - RP 0 - PCIe-B 0 - device pci 14.1 on end # - RP 1 - PCIe-B 1 + device pci 13.0 on # - RP 2 - PCIe A 0 + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[2]" = "0" + end + device pci 13.1 on # - RP 3 - PCIe A 1 + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[3]" = "0" + end + device pci 13.2 on # - RP 4 - PCIe-A 2 + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[4]" = "0" + end + device pci 13.3 on # - RP 5 - PCIe-A 3 + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[5]" = "0" + end + device pci 14.0 on # - RP 0 - PCIe-B 0 + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[0]" = "0" + end + device pci 14.1 on # - RP 1 - PCIe-B 1 + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[1]" = "0" + end device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI device pci 16.0 on # - I2C 0 |