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authorAngel Pons <th3fanbus@gmail.com>2020-11-10 20:07:33 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-11-23 12:44:20 +0000
commit28ed7878f0275ca4e2db811d3413bafc70aac830 (patch)
tree4fd1cbf4c0c2ce40245ba7882a04a1c0b20f6dd7 /src/mainboard/siemens/mc_apl1/variants/mc_apl3
parent16c06c273cf88a7fa837bbaa72392872d691f795 (diff)
mb/siemens/mc_apl1: Use `pci_or_config16` function
Change-Id: I93e09fc9801f6d32cade351bac0cba82f671acfe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: siemens-bot Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1/variants/mc_apl3')
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
index 07fa01d707..8b1a0e169f 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
@@ -22,7 +22,6 @@
void variant_mainboard_final(void)
{
struct device *dev = NULL;
- uint16_t cmd = 0;
/* PIR6 register mapping for PCIe root ports
* INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC#
@@ -43,9 +42,7 @@ void variant_mainboard_final(void)
/* Set Master Enable for on-board PCI device. */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0);
if (dev) {
- cmd = pci_read_config16(dev, PCI_COMMAND);
- cmd |= PCI_COMMAND_MASTER;
- pci_write_config16(dev, PCI_COMMAND, cmd);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream
* XIO2001 PCIe to PCI Bridge.