diff options
author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2018-09-25 10:13:47 +0200 |
---|---|---|
committer | Werner Zeh <werner.zeh@siemens.com> | 2018-09-27 15:55:46 +0000 |
commit | 7e15e87eccf8adbfdeb22dd1bca98d977c99bde1 (patch) | |
tree | 8b59921cb157342d763b870cf41b45d5ef7950b4 /src/mainboard/siemens/mc_apl1/romstage.c | |
parent | 899e2ce6ce36ab9c1a67dd480777e5c07b29951e (diff) |
siemens/mc_apl1: Make the DDR memory swizzle data configurable
In preparation for a future MC Apollo Lake board which will be equipped
with LPDDR4 modules, it is necessary to make the swizzle data
configurable. Starting from the mc_apl1 baseboard, which is equipped
with DDR3L memory and therefore does not need swizzle data, the
structures are initialized with zero.
Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1/romstage.c')
-rw-r--r-- | src/mainboard/siemens/mc_apl1/romstage.c | 103 |
1 files changed, 69 insertions, 34 deletions
diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index d56c7eedb4..87e41dc1ef 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -18,39 +18,17 @@ #include <hwilib.h> #include <lib.h> #include <string.h> +#include <soc/meminit.h> #include <soc/romstage.h> #include <fsp/api.h> #include <FspmUpd.h> #include <baseboard/variants.h> -static const uint8_t Ch0_Bit_swizzling[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -static const uint8_t Ch1_Bit_swizzling[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -static const uint8_t Ch2_Bit_swizzling[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -static const uint8_t Ch3_Bit_swizzling[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - void mainboard_memory_init_params(FSPM_UPD *memupd) { const struct pad_config *pads; + const struct lpddr4_swizzle_cfg *cfg; + const struct lpddr4_chan_swizzle_cfg *chan; uint8_t spd[0x80]; size_t num; @@ -58,7 +36,8 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); - /* Get DRAM configuration data from hwinfo block. + /* + * Get DRAM configuration data from hwinfo block. * The configuration data from hwinfo block is a one-to-one * representation of the FSPM_UPD data starting with parameter * 'Package' (offset 0x4d) and ending before parameter @@ -80,14 +59,70 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) (((uint8_t *)memupd->FspmConfig.Ch0_Bit_swizzling)- (&memupd->FspmConfig.Package))); - memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, - sizeof(Ch0_Bit_swizzling)); - memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling, - sizeof(Ch1_Bit_swizzling)); - memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling, - sizeof(Ch2_Bit_swizzling)); - memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, - sizeof(Ch3_Bit_swizzling)); + /* + * Some of the mc_apl1 boards use LPDDR4 memory. In this case, the + * correct swizzle configuration is necessary. The default settings + * for swizzling are 0, since the baseboard does not use LPDDR4 memory. + */ + cfg = variant_lpddr4_swizzle_config(); + + /* + * CH0_DQB byte lanes in the bit swizzle configuration field are + * not 1:1. The mapping within the swizzling field is: + * indices [0:7] - byte lane 1 (DQS1) DQ[8:15] + * indices [8:15] - byte lane 0 (DQS0) DQ[0:7] + * indices [16:23] - byte lane 3 (DQS3) DQ[24:31] + * indices [24:31] - byte lane 2 (DQS2) DQ[16:23] + */ + chan = &cfg->phys[LP4_PHYS_CH0B]; + memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[0], &chan->dqs[LP4_DQS1], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[8], &chan->dqs[LP4_DQS0], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[16], &chan->dqs[LP4_DQS3], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[24], &chan->dqs[LP4_DQS2], + (size_t)DQ_BITS_PER_DQS); + + /* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1. */ + chan = &cfg->phys[LP4_PHYS_CH0A]; + memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[0], &chan->dqs[LP4_DQS0], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[8], &chan->dqs[LP4_DQS1], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[16], &chan->dqs[LP4_DQS2], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[24], &chan->dqs[LP4_DQS3], + (size_t)DQ_BITS_PER_DQS); + + /* + * CH1_DQB byte lanes in the bit swizzle configuration field are + * not 1:1. The mapping within the swizzling field is: + * indices [0:7] - byte lane 1 (DQS1) DQ[8:15] + * indices [8:15] - byte lane 0 (DQS0) DQ[0:7] + * indices [16:23] - byte lane 3 (DQS3) DQ[24:31] + * indices [24:31] - byte lane 2 (DQS2) DQ[16:23] + */ + chan = &cfg->phys[LP4_PHYS_CH1B]; + memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[0], &chan->dqs[LP4_DQS1], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[8], &chan->dqs[LP4_DQS0], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[16], &chan->dqs[LP4_DQS3], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[24], &chan->dqs[LP4_DQS2], + (size_t)DQ_BITS_PER_DQS); + + /* CH1_DQA byte lanes in the bit swizzle configuration field are 1:1. */ + chan = &cfg->phys[LP4_PHYS_CH1A]; + memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[0], &chan->dqs[LP4_DQS0], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[8], &chan->dqs[LP4_DQS1], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[16], &chan->dqs[LP4_DQS2], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[24], &chan->dqs[LP4_DQS3], + (size_t)DQ_BITS_PER_DQS); memupd->FspmConfig.MsgLevelMask = 0x0; memupd->FspmConfig.MrcDataSaving = 0x0; |