mb/siemens/{mc_apl1,...,mc_apl6}: Configure FSP-S UPDs

Until now some FSP-S parameters were configured for Siemens APL
mainboards via the Binary Configuration Tool (BCT). For simplification,
the original APL FSP binary should now be used. For this purpose, the
corresponding FSP-S parameters are set via devicetree, respectively via
mainboard_silicon_init_params accordingly.

The following parameters are affected:
- Disable CPU power states (C-states)
- Set lowest Max Pkg Cstate - PkgC0C1
- Disable PCIe Hot Plug for all enabled RPs
- Disable PCIe Transmitter Half Swing for all RPs
- Disable PCIe Active State Power Management (ASPM) for all RPs
- Disable PCIe L1 Substates for all RPs

TEST:
- Compare old with new coreboot log on mc_apl5, found no differences
- Boot Linux v4.4 and check output of 'lspci'

Change-Id: I5af627defd6426140cc9a74bb18db400a8971d72
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

1 files changed, 24 insertions, 0 deletions

diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c
index b2cd449b87..bca0cbb4c8 100644
--- a/src/mainboard/siemens/mc_apl1/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/mainboard.c
@@ -12,6 +12,7 @@
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/systemagent.h>
 #include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 #include <string.h>
 #include <timer.h>
 #include <timestamp.h>
@@ -173,6 +174,29 @@ static void config_pmic_imon(void)
 	printk(BIOS_DEBUG, "PMIC: Configure PMIC IMON - End\n");
 }
 
+void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig)
+{
+	printk(BIOS_DEBUG, "MAINBOARD: %s/%s called\n", __FILE__, __func__);
+
+	/* Disable CPU power states (C-states) */
+	silconfig->EnableCx = 0;
+
+	/* Set max Pkg Cstate to PkgC0C1 */
+	silconfig->PkgCStateLimit = 0;
+
+	/* Disable PCIe Transmitter Half Swing for all RPs */
+	memset(silconfig->PcieRpTransmitterHalfSwing, 0,
+			sizeof(silconfig->PcieRpTransmitterHalfSwing));
+
+	/* Disable PCI Express Active State Power Management for all RPs */
+	memset(silconfig->PcieRpAspm, 0,
+			sizeof(silconfig->PcieRpAspm));
+
+	/* Disable PCI Express L1 Substate for all RPs */
+	memset(silconfig->PcieRpL1Substates, 0,
+			sizeof(silconfig->PcieRpL1Substates));
+}
+
 static void mainboard_init(void *chip_info)
 {
 	const struct pad_config *pads;