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authorFelix Held <felix-coreboot@felixheld.de>2022-06-13 17:19:04 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-06-14 16:35:22 +0000
commit1acb133e2d76a285f42198f0daba0f3ab16dc82c (patch)
tree661fbc0d2f7f0d5a7b805ae81c7a9ca27465f9f8 /src/mainboard/siemens/chili
parent68305aa3b0fb5e8b3213baa99d48238e57bad2ad (diff)
mb/amd/chausie/devicetree: add PCIe clock output configuration
The general purpose PCIe clock outputs 0, 1 and 3 are used with their corresponding clock request pins, so set the gpp_clk_config to GPP_CLK_REQ for those and disable the unused output 2. This matches the DXIO descriptor in port_descriptors.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I38ab8d6d824617509fdd18f06d5593889ec50666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65112 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens/chili')
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