diff options
author | Felix Singer <felixsinger@posteo.net> | 2020-12-06 05:04:22 +0100 |
---|---|---|
committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-08 20:49:54 +0000 |
commit | 0f0206c17cbb1be18c80ff979b06091b3659042d (patch) | |
tree | affe38de087dcbe327311241188d36b7c24d1507 /src/mainboard/siemens/chili/variants/base/devicetree.cb | |
parent | 8271cce95915d4f6d496d684c2654235bef55e62 (diff) |
mb/siemens/chili: Remove unnecessary device declarations
Change-Id: I193aea7c92f340bd80a41a3777bcddc3f1339620
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/siemens/chili/variants/base/devicetree.cb')
-rw-r--r-- | src/mainboard/siemens/chili/variants/base/devicetree.cb | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 196cd81359..6bdec658cf 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -86,8 +86,7 @@ chip soc/intel/cannonlake register "PcieRpSlotImplemented[5]" = "0" end device pci 1c.6 on # PCI Express Port 7 - device pci 00.0 on end # x1 M.2 (WLAN / BT) - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "1" # x1 M.2 (WLAN / BT) register "PcieRpSlotImplemented[6]" = "1" end device pci 1c.7 off end # PCI Express Port 8 @@ -100,8 +99,7 @@ chip soc/intel/cannonlake device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 device pci 1b.0 on # PCI Express Port 17 - device pci 00.0 on end # x4 M.2/M - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "1" # x4 M.2/M register "PcieClkSrcUsage[7]" = "16" register "PcieClkSrcClkReq[7]" = "7" register "PcieRpSlotImplemented[16]" = "1" |