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authorFelix Held <felix-coreboot@felixheld.de>2023-01-24 01:00:08 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-01-31 16:40:13 +0000
commita7b922fd74d754f07d95dd6bdf5afc5284b08b5f (patch)
tree8e96125287cf348e17a8e1b45857b13655e56997 /src/mainboard/sapphire
parent9f3c6ad66f8f73422ef626b3dcde1bd975f7ee76 (diff)
soc/amd/common/block/include/acpi: drop MMIO_ACPI_CPU_CONTROL define
This register isn't used in coreboot and isn't defined in the Picasso PPR #55570 Rev 3.18. To enter a lower C-state, a read request to a special IO port is done. The base address of this group of IO ports is configured in set_cstate_io_addr via the MSR_CSTATE_ADDRESS and that read won't leave the CPU. IIRC trying to put the MMIO mapping for entering the lower C-states into the _CST package didn't work as expected when it was tried on I think Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib189993879feaa0a22f6810c4bd5c1a0bc8c5a27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/sapphire')
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