mainboard: Add Sapphire Pure Platinum H61

This board has a socketed SOIC-8 4 MB flash chip. All the flash
regions are unlocked by default but unfortunately flashrom
doesn't work with the original firmware and the stock UEFI flash
tool refuses to flash the coreboot image (different image ID).
For now, the external programmer seems to be the only option for
the first coreboot flashing.

Tested and working:
 * Debian GNU/Linux Stretch (with Linux kernel 4.9, SeaBIOS)
 * Microsoft Windows 7 installer with VGA blob (SeaBIOS)
 * Internal GPU, both with VGA blob and libgfxinit (VGA and DVI)
 * External GPU
 * RAM (tested 8 + 8 GB)
 * S3
 * USB, both the 2.0 and 3.0 ports
 * Sata
 * Thermal management
 * Sound
 * LAN
 * Bluetooth
 * VT-x and VT-d
 * me_cleaner

Not working:
 * Microsoft Windows 7 installer with libgfxinit

Untested:
 * Backside Mini PCI-E port
 * DisplayPort and HDMI ports

Issues:
 * The USB is always powered, even is S3 and S5 (like in the
    original firmware).
 * Internal flashing with flashrom doesn't work after resuming
    from S3.
 * The raminit is unreliable, as the RAM training sometimes fails
    and sometimes succeeds, with the same couple of RAMs. Once
    a MRC cache has been created, the raminit works fine.
 * If an external card is inserted and the option
    ONBOARD_VGA_IS_PRIMARY is not enabled, the internal GPU
    disappears completely from the PCI bus.

Change-Id: I76aca2cfc4708c1728ae03ee4f6bc59d976c28a0
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18564
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

1 files changed, 46 insertions, 0 deletions

diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl
new file mode 100644
index 0000000000..eb98bb29bc
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Nicola Corna <nicola@corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x03,		// DSDT revision: ACPI v3.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20141018	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+	#include <cpu/intel/model_206ax/acpi/cpu.asl>
+	#include <southbridge/intel/bd82x6x/acpi/platform.asl>
+	/* global NVS and variables.  */
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+	#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+		#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+		}
+	}
+}