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authorArthur Heymans <arthur@aheymans.xyz>2022-11-12 14:51:49 +0100
committerPaul Fagerburg <pfagerburg@chromium.org>2023-02-04 01:42:39 +0000
commitb5df65a9aaee50421913ace6d7a4b35e0ddff676 (patch)
treeaa885e29c4e724f4fb583bca5c93fe1243e95da2 /src/mainboard/samsung
parent9ce7935b490830a709c62e271bf269801520ec29 (diff)
mb/*: Replace SNB PCI devices with references from chipset.cb
Removing default on/off from mainboard devicetrees is left as a follow-up. Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/mainboard/samsung')
-rw-r--r--src/mainboard/samsung/lumpy/devicetree.cb48
-rw-r--r--src/mainboard/samsung/stumpy/devicetree.cb48
2 files changed, 48 insertions, 48 deletions
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
index 4049709d52..681dfd8214 100644
--- a/src/mainboard/samsung/lumpy/devicetree.cb
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -21,8 +21,8 @@ chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x1ae0 0xc000 inherit
- device pci 00.0 on end # host bridge
- device pci 02.0 on end # vga controller
+ device ref host_bridge on end # host bridge
+ device ref igd on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# GPI routing
@@ -40,24 +40,24 @@ chip northbridge/intel/sandybridge
register "gen2_dec" = "0x003c0b01"
register "gen3_dec" = "0x00fc1601"
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT
- device pci 19.0 off end # Intel Gigabit Ethernet
- device pci 1a.0 on end # USB2 EHCI #2
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe Port #1 (WLAN)
- device pci 1c.1 off end # PCIe Port #2
- device pci 1c.2 off end # PCIe Port #3
- device pci 1c.3 on end # PCIe Port #4 (LAN)
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 off end # PCIe Port #7
- device pci 1c.7 off end # PCIe Port #8
- device pci 1d.0 on end # USB2 EHCI #1
- device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on # LPC bridge
+ device ref mei1 on end # Management Engine Interface 1
+ device ref mei2 off end # Management Engine Interface 2
+ device ref me_ide_r off end # Management Engine IDE-R
+ device ref me_kt off end # Management Engine KT
+ device ref gbe off end # Intel Gigabit Ethernet
+ device ref ehci2 on end # USB2 EHCI #2
+ device ref hda on end # High Definition Audio
+ device ref pcie_rp1 on end # PCIe Port #1 (WLAN)
+ device ref pcie_rp2 off end # PCIe Port #2
+ device ref pcie_rp3 off end # PCIe Port #3
+ device ref pcie_rp4 on end # PCIe Port #4 (LAN)
+ device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp6 off end # PCIe Port #6
+ device ref pcie_rp7 off end # PCIe Port #7
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref ehci1 on end # USB2 EHCI #1
+ device ref pci_bridge off end # PCI bridge
+ device ref lpc on # LPC bridge
chip superio/smsc/mec1308
device pnp 2e.1 on # PM1
io 0x60 = 0xb00
@@ -83,10 +83,10 @@ chip northbridge/intel/sandybridge
device pnp 0c31.0 on end
end
end
- device pci 1f.2 on end # SATA Controller 1
- device pci 1f.3 on end # SMBus
- device pci 1f.5 off end # SATA Controller 2
- device pci 1f.6 on end # Thermal
+ device ref sata1 on end # SATA Controller 1
+ device ref smbus on end # SMBus
+ device ref sata2 off end # SATA Controller 2
+ device ref thermal on end # Thermal
end
end
end
diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb
index b348f140cc..4147b160d4 100644
--- a/src/mainboard/samsung/stumpy/devicetree.cb
+++ b/src/mainboard/samsung/stumpy/devicetree.cb
@@ -20,8 +20,8 @@ chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x1ae0 0xc000 inherit
- device pci 00.0 on end # host bridge
- device pci 02.0 on end # vga controller
+ device ref host_bridge on end # host bridge
+ device ref igd on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# GPI routing
@@ -37,24 +37,24 @@ chip northbridge/intel/sandybridge
# SuperIO range is 0x700-0x73f
register "gen2_dec" = "0x003c0701"
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT
- device pci 19.0 off end # Intel Gigabit Ethernet
- device pci 1a.0 on end # USB2 EHCI #2
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe Port #1 (WLAN)
- device pci 1c.1 off end # PCIe Port #2
- device pci 1c.2 on end # PCIe Port #3 (Debug)
- device pci 1c.3 on end # PCIe Port #4 (LAN)
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 off end # PCIe Port #7
- device pci 1c.7 off end # PCIe Port #8
- device pci 1d.0 on end # USB2 EHCI #1
- device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on # LPC bridge
+ device ref mei1 on end # Management Engine Interface 1
+ device ref mei2 off end # Management Engine Interface 2
+ device ref me_ide_r off end # Management Engine IDE-R
+ device ref me_kt off end # Management Engine KT
+ device ref gbe off end # Intel Gigabit Ethernet
+ device ref ehci2 on end # USB2 EHCI #2
+ device ref hda on end # High Definition Audio
+ device ref pcie_rp1 on end # PCIe Port #1 (WLAN)
+ device ref pcie_rp2 off end # PCIe Port #2
+ device ref pcie_rp3 on end # PCIe Port #3 (Debug)
+ device ref pcie_rp4 on end # PCIe Port #4 (LAN)
+ device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp6 off end # PCIe Port #6
+ device ref pcie_rp7 off end # PCIe Port #7
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref ehci1 on end # USB2 EHCI #1
+ device ref pci_bridge off end # PCI bridge
+ device ref lpc on # LPC bridge
chip superio/ite/it8772f
# Enable GPIO10 as USBPWRON12#
# Enable GPIO12 as USBPWRON13#
@@ -102,10 +102,10 @@ chip northbridge/intel/sandybridge
device pnp 0c31.0 on end
end
end
- device pci 1f.2 on end # SATA Controller 1
- device pci 1f.3 on end # SMBus
- device pci 1f.5 off end # SATA Controller 2
- device pci 1f.6 on end # Thermal
+ device ref sata1 on end # SATA Controller 1
+ device ref smbus on end # SMBus
+ device ref sata2 off end # SATA Controller 2
+ device ref thermal on end # Thermal
end
end
end