diff options
author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-27 23:20:58 +0200 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-30 23:09:26 +0200 |
commit | e1ae4b212fd11fa9ae838afa2c045855a128e496 (patch) | |
tree | 022e821951b12b3f34716d12c8f5d44637268f1b /src/mainboard/samsung/stumpy/devicetree.cb | |
parent | 155e9b5533131f4b944ebb7e5714a871a1294dda (diff) |
Add support for Sandybridge base Samsung ChromeBox
Change-Id: Ic93ad2749834c8f7a2ca1651d343561f2a496312
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/953
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/samsung/stumpy/devicetree.cb')
-rw-r--r-- | src/mainboard/samsung/stumpy/devicetree.cb | 126 |
1 files changed, 126 insertions, 0 deletions
diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb new file mode 100644 index 0000000000..f10b283626 --- /dev/null +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -0,0 +1,126 @@ +chip northbridge/intel/sandybridge + + # Enable DisplayPort 1 Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable DisplayPort 0 Hotplug with 6ms pulse + register "gpu_dp_c_hotplug" = "0x06" + + # Enable DVI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + device lapic_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) + register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) + register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + device pci_domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi1_routing" = "0" + register "gpi14_routing" = "2" + + register "ide_legacy_combined" = "0x0" + register "sata_ahci" = "0x1" + register "sata_port_map" = "0x3" + + # SuperIO range is 0x700-0x73f + register "gen2_dec" = "0x003c0701" + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 (WLAN) + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 (Debug) + device pci 1c.3 on end # PCIe Port #4 (LAN) + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/ite/it8772f + # Enable GPIO10 as USBPWRON12# + # Enable GPIO12 as USBPWRON13# + register "gpio_set1" = "0x05" + # Enable GPIO22 as SIO_WAEKSCI# + register "gpio_set2" = "0x04" + # Enable GPIO32 as SIO_EXTSMI# + register "gpio_set3" = "0x04" + # Enable GPIO45 as LED_POWER# + register "gpio_set4" = "0x20" + # Enable GPIO51 as USBPWRON8# + # Enable GPIO52 as USBPWRON1# + register "gpio_set5" = "0x06" + # Skip keyboard init + register "skip_keyboard" = "1" + # Enable PECI on TMPIN3 + register "peci_tmpin" = "3" + # Enable FAN3 + register "fan3_enable" = "1" + + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x2f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x700 + io 0x62 = 0x710 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x720 + io 0x62 = 0x730 + end + device pnp 2e.5 on + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end # Keyboard + device pnp 2e.6 on + irq 0x70 = 12 + end # Mouse + device pnp 2e.a off end # IR + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end |