diff options
| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-27 23:19:58 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-30 23:09:10 +0200 |
| commit | 155e9b5533131f4b944ebb7e5714a871a1294dda (patch) | |
| tree | 6d3cbc7a1442648560f94675a34268bbe1671e17 /src/mainboard/samsung/lumpy/devicetree.cb | |
| parent | 6651da3bcd51ad6ea918c21564eb505b76c8c7aa (diff) | |
Add support for Sandybridge based Samsung ChromeBook
Change-Id: I8bf439bc903c1ec105016866753c7cb9ccfe5974
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/952
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/samsung/lumpy/devicetree.cb')
| -rw-r--r-- | src/mainboard/samsung/lumpy/devicetree.cb | 111 |
1 files changed, 111 insertions, 0 deletions
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb new file mode 100644 index 0000000000..36af1cae32 --- /dev/null +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -0,0 +1,111 @@ +chip northbridge/intel/sandybridge + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as LVDS and configure power delays + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms + register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms + register "gpu_panel_power_down_delay" = "150" # T3: 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms + + device lapic_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + # Coordinate with HW_ALL + register "pstate_coord_type" = "0xfe" + + register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + device pci_domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "alt_gp_smi_en" = "0x0002" + register "gpi1_routing" = "1" + register "gpi7_routing" = "2" + + register "ide_legacy_combined" = "0x0" + register "sata_ahci" = "0x1" + register "sata_port_map" = "0x1" + + # EC range is 0xa00-0xa3f + register "gen1_dec" = "0x003c0a01" + register "gen2_dec" = "0x003c0b01" + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 (WLAN) + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 (LAN) + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/smsc/mec1308 + device pnp 2e.1 on # PM1 + io 0x60 = 0xb00 + end + device pnp 2e.2 off end # EC1 + device pnp 2e.3 off end # EC2 + device pnp 2e.4 off end # UART + device pnp 2e.7 on # KBC + irq 0x70 = 1 + end + device pnp 2e.8 on # EC0 + io 0x60 = 0x62 + end + device pnp 2e.9 on # MBX + io 0x60 = 0xa00 + end + end + chip ec/smsc/mec1308 + register "mailbox_port" = "0xa00" + device pnp ff.1 off end + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end |